Prev: MAKE UPTO $5000 MONTHLY! $2000 INYOUR FIRST 30 DAYS!
Next: C2C interface from TI
From: primiano on 16 Jul 2010 06:44
Hello everyone,
I have a (maybe) simple problem I don't know exactly how to face up.

I am given a digital schematic design (which is made by a third person)
that realizes simple bus peripherals inside a Altera MAX CPLD.
The design is quite simple: the address bus along with the data bus and the
READ signals are brought as inputs of the CPLD (outputs are not considered
here).
There is a combinatorial network which, starting from the adresses and the
READ signal of the bus, derives some internal Chip Select signals used to
drive the Clock of FFD registries.

Now, I am asked to perform timing analysis to such design to verify if it
is feasible (I have the timing specs of the bus).
How can I perform such kind of *asynchronous* analysis? I am used to
analyze pure synchronous circuits, but this situation is totally
different!
Theoretically, I should verify that the propagation delay of the
combinatorial decoding network is compatible with the timings of the FFDs,
but actually I do not know exactly the timings of the FFD (I suppose they
are not a fixed value but depend on the decisions of the place and route)

Paradoxically, I would be able to verify timings if the FFDs were realized
as physical chips OFF the CPLD (verifying that the pin-to-pin combinatorial
delay is feasible according to the external FFD chips timings).

How should I model such constrains when everything is modeled inside a
CPLD? I am currently using Quartus II tools.

Thank you in advance,
Primiano Tucci

--
Primiano Tucci
http://www.primianotucci.com




---------------------------------------
Posted through http://www.EmbeddedRelated.com
From: Chris Maryan on 16 Jul 2010 09:35
If I understand you correctly, you have a combinatorial design in a
CPLD that is designed to sit in the middle of a bus and translate
between two devices. And you want to know if the timing will hold up.

Compile the CPLD and look at the timing analysis - that should give
you a input to output delay (you may have to dig through the compiler
settings to get it to produce the kind of timing report you need, last
time I checked the Altera tools gave you this with the default timing
analyzer settings). Take that number for every relevant combination of
input and output signals and you get a propagation delay from input A
to output B. Add that Tpd and add it to the Tpd in your timing
analysis, then check setup and hold as per usual.

Chris

On Jul 16, 6:44 am, "primiano" <p.tucci(a)n_o_s_p_a_m.gmail.com> wrote:
> Hello everyone,
> I have a (maybe) simple problem I don't know exactly how to face up.
>
> I am given a digital schematic design (which is made by a third person)
> that realizes simple bus peripherals inside a Altera MAX CPLD.
> The design is quite simple: the address bus along with the data bus and the
> READ signals are brought as inputs of the CPLD (outputs are not considered
> here).
> There is a combinatorial network which, starting from the adresses  and the
> READ signal of the bus, derives some internal Chip Select signals used to
> drive the Clock of FFD registries.
>
> Now, I am asked to perform timing analysis to such design to verify if it
> is feasible (I have the timing specs of the bus).
> How can I perform such kind of *asynchronous* analysis? I am used to
> analyze pure synchronous circuits, but this situation is totally
> different!
> Theoretically, I should verify that the propagation delay of the
> combinatorial decoding network is compatible with the timings of the FFDs,
> but actually I do not know exactly the timings of the FFD (I suppose they
> are not a fixed value but depend on the decisions of the place and route)
>
> Paradoxically, I would be able to verify timings if the FFDs were realized
> as physical chips OFF the CPLD (verifying that the pin-to-pin combinatorial
> delay is feasible according to the external FFD chips timings).
>
> How should I model such constrains when everything is modeled inside a
> CPLD? I am currently using Quartus II tools.
>
> Thank you in advance,
> Primiano Tucci
>
> --
>  Primiano Tucci
>  http://www.primianotucci.com
>
> ---------------------------------------        
> Posted throughhttp://www.EmbeddedRelated.com

From: Chris Maryan on 16 Jul 2010 09:47
On Jul 16, 9:35 am, Chris Maryan <kmar...(a)gmail.com> wrote:
> If I understand you correctly, you have a combinatorial design in a

Sorry, I didn't read your post in full. I thought the CPLD design was
entirely combinatorial.

Your timing will be valid for a given compile, so your clock to out
timing of the FF (which most timing analyzers can also translate to
clock to output pin timing) will only be valid for a particular case.
You can analyze that and see what your setup/hold margin is. If it's
many ns, then you're probably ok for most compiles (timing can only
vary by so much in a small CPLD). For a slow enough bus, it's usually
enough to make this hand waving argument. In an FPGA, you can usually
lock the output FFs into the output blocks (IOBs in Xilinx FPGAs), so
the timing is fixed for a given IO standard and clock setup, that's
usually good enough for most synchronous bus cases; but I don't think
CPLDs have this ability. Failing that, you can also look at the
OFFSET_IN and OFFSET_OUT constraints (at least that's what they are
called by Xilinx) that constrain the timing between the FF and the
pin; but I've never come across a case where this is needed on a well
designed board with IO block locked FFs.

Chris
 | 
Pages: 1
Prev: MAKE UPTO $5000 MONTHLY! $2000 INYOUR FIRST 30 DAYS!
Next: C2C interface from TI