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From: Rob Gaddi on 10 Feb 2010 12:07
On Tue, 09 Feb 2010 20:11:02 -0600
"Pallavi" <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote:

> Hi,
>
> I'm implementing this project where I've to generate higher output clk
> frequencies using DCM module. I have used a counter for delay
> generator, for propagation delays(Pls suggest if there is any other
> method). I have also instantiated the DCM module with an input freq
> of 50MHz and an output frequency of 320 MHz. I dont know how to write
> the test bench for this(or how to connect the DCM logic to the
> propagation delays to get higher output clock frequencies). I'm new
> to this technology and would highly appreciate if anyone could help
> me with this. the instantiation template is:
> dcm1 instance_name (
> .CLKIN_IN(CLKIN_IN),
> .RST_IN(RST_IN),
> .CLKFX_OUT(CLKFX_OUT),
> .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
> .CLK0_OUT(CLK0_OUT),
> .LOCKED_OUT(LOCKED_OUT)
> );
> and the counter logic is:
> module Counter(Clock, Direction, Count_Out);
> input Clock;
> input Direction;
> output [3:0] Count_Out;
> reg [3:0] count_int = 0;
> always @(posedge Clock)
> if (Direction)
> count_int <= count_int + 1;
> else
> count_int <= count_int - 1;
>
> assign Count_Out = count_int;
> endmodule
>

I know I'm going to regret this. I know you're going to wind up being
some student misunderstanding some inane assignment. But I'm feeling
charitable today and so, against my better judgement, I'm going to try
to walk you back out of the woods.

You're saying you need to generate higher output clock frequencies and
have delays? Why? What is it you're actually trying to design here?
I'm making the possibly over-generous assumption here that you're not
simply throwing logic blocks together in random assortments; what's the
actual goal that you're hoping to wind up with? Because so far what
you're saying doesn't make any sense. Take a step back, describe what
the project is, and maybe someone will be able to get you pointed in
the right direction.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
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