Traversing hierarchy in UCF works for OBUF, but not IOBUF, please help
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From: Ed McGettigan on 9 Sep 2009 13:22 On Sep 9, 7:46 am, Telenochek <elet.mir...(a)gmail.com> wrote: > I would prefer to avoid bringing all the ports to top level. > > I should be able to LOC constrain any internal signal of choice? IMHO not bring your IO to the level is a mistake for the following reasons - Signals that aren't used or driven are usually removed from the design during synthesis - Synthesis won't "know" to insert IO buffers on these nets requiring the IO buffers to be instantiated in the HDL - System level simulation won't be possible as the IOs are not accessible Ed McGettigan -- Xilinx Inc.
From: Telenochek on 10 Sep 2009 01:35 Not really helpful with the original question, unfortunately. Xilinx MIG (memory interface generator) hides I/Os deep in the design hierarchy. Too bad I don't have access to the code to see what the proper syntax is. "System level simulation won't be possible as the IOs are not accessible" Sorry to correct you here, but attaching SDRAM simulation models to dedicated internal controller blocks is even easier than to the top level. Finally, making the design internal makes it much more portable, as you can simply pass the controller interface with instantiated I/O buffers and I/O to one of your engineers, and they never have to do anything but work with the interface. BTW, Xilinx realized recently that this is much more advantageous from hardware standpoint than the ancient top level driven designs: the latest ISE 10 allows multiple .ucf files for this reason.
From: Telenochek on 10 Sep 2009 01:35 Not really helpful with the original question, unfortunately. Xilinx MIG (memory interface generator) hides I/Os deep in the design hierarchy. Too bad I don't have access to the code to see what the proper syntax is. "System level simulation won't be possible as the IOs are not accessible" Sorry to correct you here, but attaching SDRAM simulation models to dedicated internal controller blocks is even easier than to the top level. Finally, making the design internal makes it much more portable, as you can simply pass the controller interface with instantiated I/O buffers and I/O to one of your engineers, and they never have to do anything but work with the interface. BTW, Xilinx realized recently that this is much more advantageous from hardware standpoint than the ancient top level driven designs: the latest ISE 10 allows multiple .ucf files for this reason.
From: Ed McGettigan on 10 Sep 2009 02:09
On Sep 9, 10:35 pm, Telenochek <elet.mir...(a)gmail.com> wrote: > Not really helpful with the original question, unfortunately. > > Xilinx MIG (memory interface generator) hides I/Os deep in the design > hierarchy. > Too bad I don't have access to the code to see what the proper syntax > is. > > "System level simulation won't be possible as the IOs are not > accessible" > Sorry to correct you here, but attaching SDRAM simulation models to > dedicated internal controller blocks is even easier than to the top > level. > > Finally, making the design internal makes it much more portable, as > you can simply pass the controller interface with instantiated I/O > buffers and I/O to one of your engineers, and they never have to do > anything but work with the interface. > > BTW, Xilinx realized recently that this is much more advantageous from > hardware standpoint than the ancient top level driven designs: the > latest ISE 10 allows multiple .ucf files for this reason. Actually, I think that the suggestion to bring the IO ports to the top level is helpful to your orginal question as it appears that the net name on the IO port of the IOBUF is different than you expected it to be and this would solve the problem. One addition suggestion, since you don't want to propogate the signal then try adding the LOC to the instance name which likely has not changed. INST "eight_chan_gen/u1/external_sdram/U1/IOBUF_inst0" LOC = "A4"; With respect to your comments on the MIG output, the physical level interface is presented on the core interface with the intent that nets are connected to the top level ports in the design. This is shown in all of the design examples. I have no idea how "attaching SDRAM simulation models to the dedicated internal memory blocks" is easier. Please elaborate on why this is easier to use and maintain between simulation and synthesis. Ed McGettigan -- Xilinx Inc. |