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From: ghelbig on 18 Dec 2009 18:52
My apologies if this has been addressed - my web searches came up
empty.

I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
clock and a 1/2-X clock.

The output of the DCM goes to a BUFG. The output of the BUFG goes to
the feedback pin of the DCM, and to the rest of the logic.

After initialization, the input clock changes frequency. Shortly
after that, I send a reset (7 clock wide) to the DCM.

The locked signal from the DCM goes away about 22uS after the input
clock changes. I see a short pulse on status[1] indicating that it
didn't like the input clock, and 22uS later Locked goes low.

About 20uS after that, I send the reset pulse to the DCM. Locked
never (never) goes high again.

The output clock is present, but the logic is behaving like the
warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
spurious behavior") is very true.

Any clues, hints, sympathy?

Redards,
Gary.
From: Patrick Maupin on 19 Dec 2009 00:56
On Dec 18, 5:52 pm, ghelbig <ghel...(a)lycos.com> wrote:
> My apologies if this has been addressed - my web searches came up
> empty.
>
> I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
> clock and a 1/2-X clock.
>
> The output of the DCM goes to a BUFG.  The output of the BUFG goes to
> the feedback pin of the DCM, and to the rest of the logic.
>
> After initialization, the input clock changes frequency.  Shortly
> after that, I send a reset (7 clock wide) to the DCM.
>
> The locked signal from the DCM goes away about 22uS after the input
> clock changes.  I see a short pulse on status[1] indicating that it
> didn't like the input clock, and 22uS later Locked goes low.
>
> About 20uS after that, I send the reset pulse to the DCM.  Locked
> never (never) goes high again.
>
> The output clock is present, but the logic is behaving like the
> warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
> spurious behavior") is very true.

Is the new input clock frequency within the valid frequency range for
using feedback? (That range is a lot smaller than if you are only
using the DFS).

Also, I know Xilinx says it will reset after 4 clocks, but for some
reason I always seem to reset for longer than that. Can't remember if
I've ever been burned or if it just seemed to work out that way.

Regards,
Pat


From: John Adair on 19 Dec 2009 05:36
Don't rely on the locked signal for anything. Use the status lines and
make your own locked signal.

The DCM does take a while to fully lock up during which time you will
get strange frequencies and strange mark/space ratios. If you are
trying to do something like a power saving frequency switch you might
be better either to use clock enables to change effective clock rate
or alternatively using an external synthesiser that supports these
sort of frequency changes a bit more elegantly.

John Adair
Enterpoint Ltd.- Home of Merrick1. The Data Mining Solution.


On 18 Dec, 23:52, ghelbig <ghel...(a)lycos.com> wrote:
> My apologies if this has been addressed - my web searches came up
> empty.
>
> I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
> clock and a 1/2-X clock.
>
> The output of the DCM goes to a BUFG.  The output of the BUFG goes to
> the feedback pin of the DCM, and to the rest of the logic.
>
> After initialization, the input clock changes frequency.  Shortly
> after that, I send a reset (7 clock wide) to the DCM.
>
> The locked signal from the DCM goes away about 22uS after the input
> clock changes.  I see a short pulse on status[1] indicating that it
> didn't like the input clock, and 22uS later Locked goes low.
>
> About 20uS after that, I send the reset pulse to the DCM.  Locked
> never (never) goes high again.
>
> The output clock is present, but the logic is behaving like the
> warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
> spurious behavior") is very true.
>
> Any clues, hints, sympathy?
>
> Redards,
> Gary.

From: ghelbig on 19 Dec 2009 12:25
Details I should have included:

The external clock is a synthesizer that defaults to 50MHz. After
initialization, it is changed to 100MHz. The DCM is used to reduce
the skew between the internal clock and the external clock and create
a half-speed clock for some of the logic.

Some percentage of the time, the chip "just don't run"; my current
theory is that the clock comes up strange.

I'm not getting anything useful from the status lines. At the time
the frequency is changed, I get a pulse on status[1]; after that, they
are always low. I've waited "forever", and the locked signal never
goes true.

Thanks!

On Dec 19, 2:36 am, John Adair <g...(a)enterpoint.co.uk> wrote:
> Don't rely on the locked signal for anything. Use the status lines and
> make your own locked signal.
>
> The DCM does take a while to fully lock up during which time you will
> get strange frequencies and strange mark/space ratios. If you are
> trying to do something like a power saving frequency switch you might
> be better either to use clock enables to change effective clock rate
> or alternatively using an external synthesiser that supports these
> sort of frequency changes a bit more elegantly.
>
> John Adair
> Enterpoint Ltd.- Home of Merrick1. The Data Mining Solution.
>
> On 18 Dec, 23:52, ghelbig <ghel...(a)lycos.com> wrote:
>
> > My apologies if this has been addressed - my web searches came up
> > empty.
>
> > I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
> > clock and a 1/2-X clock.
>
> > The output of the DCM goes to a BUFG. The output of the BUFG goes to
> > the feedback pin of the DCM, and to the rest of the logic.
>
> > After initialization, the input clock changes frequency. Shortly
> > after that, I send a reset (7 clock wide) to the DCM.
>
> > The locked signal from the DCM goes away about 22uS after the input
> > clock changes. I see a short pulse on status[1] indicating that it
> > didn't like the input clock, and 22uS later Locked goes low.
>
> > About 20uS after that, I send the reset pulse to the DCM. Locked
> > never (never) goes high again.
>
> > The output clock is present, but the logic is behaving like the
> > warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
> > spurious behavior") is very true.
>
> > Any clues, hints, sympathy?
>
> > Redards,
> > Gary.

From: John Adair on 19 Dec 2009 13:01
I would suggest holding the DCM in reset until the input clock is
stable and running at correct rate. Note also the lock times can be up
nearly 3ms in some circumstances going by the data in datasheet ds099.

John Adair
Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board.

On 19 Dec, 17:25, ghelbig <ghel...(a)lycos.com> wrote:
> Details I should have included:
>
> The external clock is a synthesizer that defaults to 50MHz.  After
> initialization, it is changed to 100MHz.  The DCM is used to reduce
> the skew between the internal clock and the external clock and create
> a half-speed clock for some of the logic.
>
> Some percentage of the time, the chip "just don't run"; my current
> theory is that the clock comes up strange.
>
> I'm not getting anything useful from the status lines.  At the time
> the frequency is changed, I get a pulse on status[1]; after that, they
> are always low.  I've waited "forever", and the locked signal never
> goes true.
>
> Thanks!
>
> On Dec 19, 2:36 am, John Adair <g...(a)enterpoint.co.uk> wrote:
>
> > Don't rely on the locked signal for anything. Use the status lines and
> > make your own locked signal.
>
> > The DCM does take a while to fully lock up during which time you will
> > get strange frequencies and strange mark/space ratios. If you are
> > trying to do something like a power saving frequency switch you might
> > be better either to use clock enables to change effective clock rate
> > or alternatively using an external synthesiser that supports these
> > sort of frequency changes a bit more elegantly.
>
> > John Adair
> > Enterpoint Ltd.- Home of Merrick1. The Data Mining Solution.
>
> > On 18 Dec, 23:52, ghelbig <ghel...(a)lycos.com> wrote:
>
> > > My apologies if this has been addressed - my web searches came up
> > > empty.
>
> > > I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
> > > clock and a 1/2-X clock.
>
> > > The output of the DCM goes to a BUFG.  The output of the BUFG goes to
> > > the feedback pin of the DCM, and to the rest of the logic.
>
> > > After initialization, the input clock changes frequency.  Shortly
> > > after that, I send a reset (7 clock wide) to the DCM.
>
> > > The locked signal from the DCM goes away about 22uS after the input
> > > clock changes.  I see a short pulse on status[1] indicating that it
> > > didn't like the input clock, and 22uS later Locked goes low.
>
> > > About 20uS after that, I send the reset pulse to the DCM.  Locked
> > > never (never) goes high again.
>
> > > The output clock is present, but the logic is behaving like the
> > > warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
> > > spurious behavior") is very true.
>
> > > Any clues, hints, sympathy?
>
> > > Redards,
> > > Gary.

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