Ultra low frequency VCO
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From: Paul Keinanen on 6 Jul 2010 16:16 On Tue, 06 Jul 2010 09:52:43 -0700, Tim Wescott <tim(a)seemywebsite.com> wrote: >On 07/06/2010 09:10 AM, Daku wrote: >> On Jul 5, 8:59 pm, Tim Wescott<t...(a)seemywebsite.com> wrote: >>> I'd hardly call 60Hz "ultra low frequency". But it is pretty darned low. >>> >>> All the suggestions you've gotten so far are good as far as they go and >>> may well be perfect -- but what are you trying to do? Do you need sine >>> wave out or square? If sine wave, how pure? Do you have any >>> specifications on jitter, phase noise, or frequency accuracy? >> I am trying to design a PLL for very low frequencies, e.g., power line >> grid. >> I am concerned with the VCO as it is a crucial sub-circuit. I am >> aiming for >> a phase noise of approximately -100 dBc/Hz but not very sure of the >> offset >> frequency. Ideally, I would like to have frequency accuracy of 1 - 5% >> at most. >> Also, I am aware that S-parameter methods are not appropriate at these >> low >> frequencies. If you want to track the _actual_ mains frequency, just use a mains driven synchronous motor. To get the noise sidebands down, use some flywheels :-). > >I think that those specs would be difficult to achieve with an >all-analog oscillator running at 60Hz. Not impossible -- I could do it, >and Joerg could do it in a fraction of the time I'd take. Using some >sort of direct digital synthesis -- even if it's just a microprocessor >-- running off of a crystal reference would be almost trivial in >comparison and would probably take less board space and would be far >more repeatable in manufacturing. > >If you just had to do this purely in the analog domain your best bet >might be a pair of crystal oscillators, frequency steered with >varactors, carefully built, and with their outputs mixed down to 60Hz. >But that's a solution I would expect to see in a bit of kit from the >50's through the 80's -- anything later and I'd expect to see a DDS. Just a few minutes ago, the Nordel AC network (Danish isles, Finland, Norway, Sweden) was running at 50.11 Hz or +2200 ppm above nominal in order to allow the mains synchronized clocks to catch up. A simple fundamental frequency VXCO can be pulled about +/-100 ppm with the load capacitance. About 1000 ppm is the maximum with adjustable serial inductance and adjustable parallel load capacitance at the crystal. At 50/60 Hz, even a trivial processor can generate a variable frequency sine wave using the NCO (Numerically Controlled Oscillator) principle to generate a sine wave, which can be locked to the incoming signal in some loop configuration. Even a trivial processor might be able to generate both sine and cosine waveforms for 49.98, 50.00. 50.92 Hz etc. in parallel and performing a phase comparison between all these in parallel to determine the best match.
From: Grant on 6 Jul 2010 18:49 On Tue, 06 Jul 2010 11:56:19 -0700, "Paul Hovnanian P.E." <paul(a)hovnanian.com> wrote: >Daku wrote: > >[snip] >> Also, I am aware that S-parameter methods are not appropriate at these >> low frequencies. > >Why not? Actual L/C component values might be a bit larger than most people >here deal with, but the math is still the same. Gyrator for the L? Grant.
From: Tim Wescott on 6 Jul 2010 19:34 On 07/06/2010 03:49 PM, Grant wrote: > On Tue, 06 Jul 2010 11:56:19 -0700, "Paul Hovnanian P.E."<paul(a)hovnanian.com> wrote: > >> Daku wrote: >> >> [snip] >>> Also, I am aware that S-parameter methods are not appropriate at these >>> low frequencies. >> >> Why not? Actual L/C component values might be a bit larger than most people >> here deal with, but the math is still the same. > > Gyrator for the L? Way noisy. You may as well use a Wien bridge oscillator. Basically the phase noise of an LC oscillator is closely related to the noise of the amplifier divided by the loaded Q of the tank circuit. In the case of an RC oscillator (i.e. anything that doesn't use a real resonant component) the 'loaded Q' is less than unity, which makes achieving that -100dBc phase noise spec difficult. (Why so low, by the way?). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
From: whit3rd on 6 Jul 2010 19:43 On Jul 6, 9:52 am, Tim Wescott <t...(a)seemywebsite.com> wrote: > > I am trying to design a PLL for very low frequencies, e.g., power line > > grid. > > I am concerned with the VCO as it is a crucial sub-circuit. I am > > aiming for > > a phase noise of approximately -100 dBc/Hz > I think that those specs would be difficult to achieve with an > all-analog oscillator running at 60Hz. Not impossible -- I could do it, An LC type oscillator is good for phase stability (multivibrator types are less good), but C values of voltage-variable capacitors are inconvenient for this range. So, you're stuck with an increductor. This is an inductor with a semi-saturating core, using a high impedance winding with DC current in it to move the inductance. It's an old technique (usually nowadays this kind of thing is only used for flux-gate magnetometers) but a goodie. Switched-capacitor filters with a 100x clock are another approach. I think the MF10 app note has an example (figure 7). <http://www.national.com/an/AN/AN-307.pdf> The fast clock can be a relatively unstable CD4046 type of VCO, it'll all average out. Hopefully.
From: JosephKK on 7 Jul 2010 07:52
On Tue, 6 Jul 2010 09:10:25 -0700 (PDT), Daku <dakupoto(a)gmail.com> wrote: >On Jul 5, 8:59 pm, Tim Wescott <t...(a)seemywebsite.com> wrote: >> I'd hardly call 60Hz "ultra low frequency". But it is pretty darned low. >> >> All the suggestions you've gotten so far are good as far as they go and >> may well be perfect -- but what are you trying to do? Do you need sine >> wave out or square? If sine wave, how pure? Do you have any >> specifications on jitter, phase noise, or frequency accuracy? >I am trying to design a PLL for very low frequencies, e.g., power line >grid. >I am concerned with the VCO as it is a crucial sub-circuit. I am >aiming for >a phase noise of approximately -100 dBc/Hz but not very sure of the >offset Yikes, it would take years (decades) to measure that. Your reference standard to measure against would be problematic as well. One cycle (about 16.667 ms) * 10^10 is over 46,000 hours, 275 weeks, 5.2 years. How about reframing it as a jitter and wander specification? >frequency. Ideally, I would like to have frequency accuracy of 1 - 5% >at most. You would blow the phase noise spec by being off by fractional millihertz. >Also, I am aware that S-parameter methods are not appropriate at these >low >frequencies. > >> >> You could digitally synthesize a 60Hz sine wave with a smallish >> processor -- I believe there are some TMS430 parts that could do it all >> in one package with a PWM output to be filtered by a simple RC. >> >> But "best" depends heavily on what you want. >> >> -- >> >> Tim Wescott >> Wescott Design Serviceshttp://www.wescottdesign.com >> >> Do you need to implement control loops in software? >> "Applied Control Theory for Embedded Systems" was written for you. >> See details athttp://www.wescottdesign.com/actfes/actfes.html |