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From: Joel Koltner on 12 Jul 2010 13:13 "Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)On-My-Web-Site.com> wrote in message news:dcim36poktoi3gc0keapvnbjlpsri0lqj4(a)4ax.com... [coaxial ceramic resonators] > I've been "using" them... designing them into GPS LO's since before > you were born ;-) What's the advantage -- for you -- over crystals? Just lower cost? ---Joel
From: Phil Hobbs on 12 Jul 2010 13:19 George Herold wrote: > On Jul 12, 11:09 am, Phil Hobbs > <pcdhSpamMeSensel...(a)electrooptical.net> wrote: >> j wrote: >>> The point is that a lot of this jiber-jaber is pointless. Without the >>> OP giving a better definition of the problem it�s a guess at best >>> which measurement technique is required. >>> He never did state the basis for his phase noise number, nor did he >>> have an offset frequency. >>> The challenge in making �100 dBc or better measurements is a function >>> of the offset frequency and bandwidth. Center frequency isn�t the >>> issue here. >> You may not be interested, but perhaps other folks are. And how big an >> offset frequency can he have on a 60 Hz carrier, anyway? >> >> Cheers >> >> Phil Hobbs >> >> -- >> Dr Philip C D Hobbs >> Principal >> ElectroOptical Innovations >> 55 Orchard Rd >> Briarcliff Manor NY 10510 >> 845-480-2058 >> hobbs at electrooptical dot nethttp://electrooptical.net > > Yes! I've enjoyed the discussion. Say could someone explain the the > 100 dBc of phase noise spec. I've been thinking of this a one part in > 10^5 of jitter in the period. So for instance a 1 Hz signal the > jitter is less than 10 micro seconds aand for a 1 MHz signal a jitter > of 10 pico seconds. > > Is that right? > > George H. Small phase jitter is the quadrature partner of small amplitude noise. Say you have a pure carrier and add ordinary white noise, e.g. by putting a resistor in series with the perfect oscillator's output. The resulting RMS phase deviation in some given bandwidth is <delta_phi> = 1/(sqrt(2*CNR)) where CNR is the carrier to noise ratio (i.e. carrier power/noise power in the given bandwidth). The factor of sqrt(2) expresses the fact that the noise and signal are uncorrelated, so that half the noise power winds up in the I phase as amplitude noise, and half winds up in the Q phase as phase noise. You can derive this from the formula for sums and differences of sines and cosines plus an orthogonality argument--it's quite pretty. It's in my section 13.6 (either edition), but that derivation almost certainly isn't original with me. One very pleasant consequence is that the phase noise statistics are the same as those of the additive noise in the high-CNR limit where the formula applies. The universality of this formula is why essentially all FM and PM detectors have equivalent performance at high SNR--where the additive model breaks down is low SNR, where FM/PM detection schemes really differ in performance. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
From: Jim Thompson on 12 Jul 2010 13:34 On Mon, 12 Jul 2010 10:13:03 -0700, "Joel Koltner" <zapwireDASHgroups(a)yahoo.com> wrote: >"Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)On-My-Web-Site.com> wrote in >message news:dcim36poktoi3gc0keapvnbjlpsri0lqj4(a)4ax.com... > >[coaxial ceramic resonators] > >> I've been "using" them... designing them into GPS LO's since before >> you were born ;-) > >What's the advantage -- for you -- over crystals? Just lower cost? > >---Joel Small, hi-Q, but reasonably pull-able, to phase lock. (Cost never matters to me, I'm never paying ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Obama isn't going to raise your taxes...it's Bush' fault: Not re- newing the Bush tax cuts will increase the bottom tier rate by 50%
From: Joel Koltner on 12 Jul 2010 13:52 "Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)On-My-Web-Site.com> wrote in message news:1ekm36hmf1f3egiu3uvg9olh3ieb0e4cq0(a)4ax.com... >>What's the advantage -- for you -- over crystals? Just lower cost? > Small, hi-Q, but reasonably pull-able, to phase lock. Ah, gotcha -- I wans't thinking (the really rather obvious bit) that there's no such thing as a 1575.42MHz crystal. :-) Speaking of PLLs... do you happen to know why so many of them have rather high (hundreds of MHz) lower frequency limits? E.g., this seemingly-popular part: http://www.national.com/pf/LM/LMX2485.html ... only goes down to 500MHz on one of the PLLs; National has a slightly different version -- http://www.national.com/pf/LM/LMX2485E.html -- that goes down to 50MHz. What's different inside, would you think? Discussions at work here and with Joerg have postulated: -- AC coupling of the input amplifiers? -- The fastest counters (dividers) are actually dynamic circuitry, and hence they really can't count too slowly or they forget where they were. (1, 2, 3... umm? 3? 1? Where was I again? La-la-la-la-la I'm so confused!) There aren't a lot of low-power PLL-based synthesizers in the "more than a handful of MHz"-CD4046 (and derivative) territory and these multi-hundred-MHz+ monsters. We're after some 45MHz PLLs, and so far the ADF4001 is one of the very few attractive-looking candidates. Thanks for the help, ---Joel
From: Jim Thompson on 12 Jul 2010 14:12
On Mon, 12 Jul 2010 10:52:10 -0700, "Joel Koltner" <zapwireDASHgroups(a)yahoo.com> wrote: >"Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)On-My-Web-Site.com> wrote in >message news:1ekm36hmf1f3egiu3uvg9olh3ieb0e4cq0(a)4ax.com... >>>What's the advantage -- for you -- over crystals? Just lower cost? >> Small, hi-Q, but reasonably pull-able, to phase lock. > >Ah, gotcha -- I wans't thinking (the really rather obvious bit) that there's >no such thing as a 1575.42MHz crystal. :-) Rather than think "resonator", think very-low-loss shorted-termination transmission line stub. (Think college days :-) > >Speaking of PLLs... do you happen to know why so many of them have rather high >(hundreds of MHz) lower frequency limits? E.g., this seemingly-popular part: >http://www.national.com/pf/LM/LMX2485.html ... only goes down to 500MHz on one >of the PLLs; National has a slightly different version -- >http://www.national.com/pf/LM/LMX2485E.html -- that goes down to 50MHz. >What's different inside, would you think? Don't know. Might be AC-coupling internally... makes dividers less prone to offset voltages at those frequencies. > >Discussions at work here and with Joerg have postulated: > >-- AC coupling of the input amplifiers? Yep. See above. >-- The fastest counters (dividers) are actually dynamic circuitry, and hence >they really can't count too slowly or they forget where they were. (1, 2, >3... umm? 3? 1? Where was I again? La-la-la-la-la I'm so confused!) Indeed ;-) > >There aren't a lot of low-power PLL-based synthesizers in the "more than a >handful of MHz"-CD4046 (and derivative) territory and these multi-hundred-MHz+ >monsters. We're after some 45MHz PLLs, and so far the ADF4001 is one of the >very few attractive-looking candidates. > >Thanks for the help, >---Joel > > I rarely keep track of OTC offerings, since I'm really in the designing whole SOC business. Occasionally a client will say, "I want all this garbage on a single chip", and hand me a pile of data sheets. Then I have to analyze how it all works. That actually works out well with usually significant space and power compaction, since I/O can use up a lot of chip area and power. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Obama isn't going to raise your taxes...it's Bush' fault: Not re- newing the Bush tax cuts will increase the bottom tier rate by 50% |