Prev: MSI for BMD design
Next: Which is the most beautiful and memorable hardware structure in a CPU?
From: gaurang4040 on 30 Mar 2010 11:47
Hi all,

I want to used parameterized Verilog macros in my code.
It looks somewhat as shown below:

////////////////////////////////////////////////////////////
`define ACTIVE_EDGE posedge
parameter ISO_SENSE=1;
always @(`ACTIVE_EDGE isolation_ctrl)
if(isolation_ctrl==ISO_SENSE)
power_iso_flag=0;
////////////////////////////////////////////////////////////


I used "tick define" macro and parameter as I need my code to be somewhat
generic.

Now, I want to extend the same for the following case:
(1) isolation_ctrl can be a vector with width N and it will have
corresponding ISO_SENSE values. That is,

logic [NO-1:0] isolation_ctrl;
bit [NO-1:0] ISO_SENCE;
(2) If ISO_SENCE[i] is 1, the macro `ACTIVE_EDGE should take value posedge.
Whereas, it should take negedge for ISO_SENCE[i]=0.

I tried to do so using generate and macro with argument as follows:


////////////////////////////////////////////////////////////
`define str1 posedge
`define str2 negedge
`define ACTIVE_ISO_EDGE(a) ( a ? `str1 : `str2 )
...
module abc ( ...);
...
...
bit [3:0] sences='{1, 0, 0, 1};
...
...
generate
genvar j;

for(i=0; i<NO_OF_DOMAINS; i++)
begin
always @( `ACTIVE_ISO_EDGE( sences[i]) isolation_ctrl[i] )
if(isolation_ctrl[i]==ISO_SENSE[i])
power_iso_flag[i]=0;
end

endgenerate
...
...
endmodule
////////////////////////////////////////////////////////////


However, it gives the following error:

Error-[SE] Syntax error
Following verilog source has syntax error :
"env/assertions.sv", 309 (expanding macro): token is 'posedge'
always @(`ACTIVE_ISO_EDGE(ds[j]) isolation_ctrl_for_all_domains[j])


Can anyone please help me solve this? I am not getting the exact way in
which I can employ macros to make everything generic along with generate.
Hoping for some useful comments. :)


Thanks,
Gaurang



---------------------------------------
Posted through http://www.FPGARelated.com
From: Jonathan Bromley on 2 Apr 2010 18:48
On Tue, 30 Mar 2010 10:47:40 -0500, "gaurang4040" wrote:

>`define str1 posedge
>`define str2 negedge
>`define ACTIVE_ISO_EDGE(a) ( a ? `str1 : `str2 )
>..
>module abc ( ...);
>..
>..
>bit [3:0] sences='{1, 0, 0, 1};
>..
>..
>generate
>genvar j;
>
> for(i=0; i<NO_OF_DOMAINS; i++)
> begin
> always @( `ACTIVE_ISO_EDGE( sences[i]) isolation_ctrl[i] )
> if(isolation_ctrl[i]==ISO_SENSE[i])
> power_iso_flag[i]=0;
> end
>
>endgenerate

No, you can't do that.

Remember that macros do source text replacement. They don't
change the source code dynamically.

If "sences" (sic) were a parameter, you could use it to control
a generate statement - far nicer than using a macro:

parameter [3:0] senses = 4'b1001;
generate
genvar i;
for (i=0; i<NO_OF_DOMAINS; i++) begin : mixed_polarities
if (senses[i]) begin : here_is_the_choice
always @(posedge isolation_ctrl[i])
power_iso_flag[i] <= 0;
end
end
endgenerate

Your original macro was generating source code that looks like...

always @(sences[i]? posedge : negedge something) ...

Clearly this is gobbledeygook and will never get through compilation.
--
Jonathan Bromley
From: Jonathan Bromley on 3 Apr 2010 06:18
On Fri, 02 Apr 2010 23:48:48 +0100, Jonathan Bromley wrote:

[evidently, whilst half asleep]

> parameter [3:0] senses = 4'b1001;
> generate
> genvar i;
> for (i=0; i<NO_OF_DOMAINS; i++) begin : mixed_polarities
> if (senses[i]) begin : here_is_the_choice
> always @(posedge isolation_ctrl[i])
> power_iso_flag[i] <= 0;
> end
> end
> endgenerate

Oh dear.

(1) the parameter needs to be the right size:

parameter [NO_OF_DOMAINS-1:0] senses = ...;

(2) I forgot the "else" branch of the flipflop generate:

> for (i=0; i<NO_OF_DOMAINS; i++) begin : mixed_polarities
> if (senses[i]) begin : here_is_the_choice
> always @(posedge isolation_ctrl[i])
> power_iso_flag[i] <= 0;
> end
else begin
always @(negedge isolation_ctrl[i])
end

Oops.
--
Jonathan Bromley
 | 
Pages: 1
Prev: MSI for BMD design
Next: Which is the most beautiful and memorable hardware structure in a CPU?