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From: Quadibloc on 12 Apr 2010 15:39
On my web page at

http://www.quadibloc.com/arch/arcint.htm

I have a description of a computer architecture which runs on for many
pages.

It combines features picked up from the IBM 360, the Cray-1, the NORC,
the Honeywell 800, and a lot of other machines, plus some features so
bizarre as never to have made it into production (an L2 cache line
contains 16 words, but you can put the computer in a mode where, when
fetching from a part of memory used for data and not instructions, it
fills only 9 of those slots in each line of the L2 cache, so that when
data goes from L2 cache to L1 cache, a maze of wires puts 36
contiguous bits of data into every 64 bits of the L1 cache, so the
computer can act as if it has a 36 bit word)...

and it also has dozens of alternate operation modes where the various
instruction formats are shuffled around.

Well, a while back, I had achieved a more satisfying level of code
density by making use of the idea of coding for aligned operands only
from the SEL 32 computer. And so I removed a few of the alternate
operation modes.

I can't say how soon this will be ready for uploading... but I am
making good progress on preparing a modification to the site where
there will now be only *one* instruction mode.

It will use the SEL 32 trick to make nearly all the common
instructions as short as one would expect them to be (i.e. not needing
a whole 16-bit prefix at the front just to distinguish them from other
contenders for the overburdened instruction space).

But *more* than that...

while it won't be quite as simple as the original IBM 360 scheme:

00xxxxxx - 16 bits long
01xxxxxx or 10xxxxxx - 32 bits long
11xxxxxx - 48 bits long

the instructions are going to be organized systematically so that it
will be possible for a level of circuitry that is only a fraction of
the complete instruction decoding circuit to determine how many 16-bit
halfwords the instruction occupies, so that by the time the next cycle
arrives, the computer will actually know where to fetch its next
instruction from.

Previously, I suppose I was just going to speculatively decode
instructions starting at every possible 16-bit boundary... hey, it's
only silicon!

So, while the architecture will still be grossly baroque and
impractical... it is about to take a giant step from being absolutely
grotesquely baroque and impractical to merely considerably baroque and
impractical!!!

John Savard
From: Jim Stewart on 12 Apr 2010 17:49
Quadibloc wrote:
> On my web page at
>
> http://www.quadibloc.com/arch/arcint.htm
>
> I have a description of a computer architecture which runs on for many
> pages.
>
> It combines features picked up from the IBM 360, the Cray-1, the NORC,
> the Honeywell 800, and a lot of other machines, plus some features so
> bizarre as never to have made it into production (an L2 cache line
> contains 16 words, but you can put the computer in a mode where, when
> fetching from a part of memory used for data and not instructions, it
> fills only 9 of those slots in each line of the L2 cache, so that when
> data goes from L2 cache to L1 cache, a maze of wires puts 36
> contiguous bits of data into every 64 bits of the L1 cache, so the
> computer can act as if it has a 36 bit word)...
>
> and it also has dozens of alternate operation modes where the various
> instruction formats are shuffled around.

What, no Linc-8 mode? This sir, is an outrage....
http://en.wikipedia.org/wiki/LINC-8
From: Al Kossow on 12 Apr 2010 18:50
On 4/12/10 2:49 PM, Jim Stewart wrote:

> What, no Linc-8 mode?

That would actually require two modes, one for LINC and one for PDP-8

From: Quadibloc on 12 Apr 2010 20:17
On Apr 12, 3:49 pm, Jim Stewart <jstew...(a)jkmicro.com> wrote:

> What, no Linc-8 mode?  This sir, is an outrage...

Well, the PDP-8, and the LINC, are discussed on my web site, at

http://www.quadibloc.com/comp/cp0306.htm
From: nedbrek on 12 Apr 2010 21:36
Hello all,

"Quadibloc" <jsavard(a)ecn.ab.ca> wrote in message
news:e80b1c12-e74e-4689-b1e2-c045a1847071(a)35g2000yqm.googlegroups.com...
[snip, a lot of crazy stuff]

I am truly impressed. Reminds me of the IA-128 file I used to keep at work
(combining all the worst parts of i860, IA64, and more bad stuff).

> a mode where, when fetching from a part of memory used for data and not
> instructions, it fills only 9 of those slots in each line of the L2 cache,
> so
> that when data goes from L2 cache to L1 cache, a maze of wires puts 36
> contiguous bits of data into every 64 bits of the L1 cache, so the
> computer can act as if it has a 36 bit word)...

Is that some sort of S/360 compatibility thing?

Ned


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