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From: rafayhasan on 5 Aug 2010 15:14
Hello All,

I am writing this to seek your guidance in knowing the possible
methods/procedures to verify the analytical SEU estmiates for an FPGA
designs. To my understanding the way to go about it is beam testing or
laser testing. The fault injection methods don't seem to me prudent in this
case as we are checking the estimate of soft errors in an FPGA design and
not verifying a mitigating methodology ?

My second query is related to the method of estimating SEU rate in Xilinx
FPGAs. I am utilizing the knowledge obtained from XDL and FPGA Editor to
make an estimate of configuration bits used by my design. The problem I am
encountering is how to estimate total configuration bits in the nets that
are related to "pips".

for example it is true that a pip connecting two nodes of a switch will
require only one configuration bit, but at the same time each node of the
switch is connected to several other nodes. Hence potentially the net may
get connected to an irrelevant node (erroneously) due to SEU. And this
leads to me the question that what should I do to cope such a scenario in
an effort to provide realistic estimate of configuration bits ?

Of course what I am doing is with publicly available information from
Xilinx and hence it should not cause any legal hitch.

Your recommendations would be highly appreciated.

Rafay




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