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From: John Fields on 30 Jan 2010 16:34
On Thu, 28 Jan 2010 18:43:08 -0800 (PST), Bill Sloman
<bill.sloman(a)ieee.org> wrote:

>On Jan 29, 2:19�am, Steve <st...(a)nomail.net> wrote:
>> On Thu, 28 Jan 2010 16:01:13 -0800 (PST), Bill Sloman
>>
>> <bill.slo...(a)ieee.org> wrote:
>> >A 24-bit sigma-delta D/A converter from Burr-Brown (now part of TI)
>> >turned out to be pretty attractive; for the slow rates I was planning
>>
>> looks like 20 bits is the best they do now (DAC1220)
>
>Oops. I was relying on my memory, and it was ten years ago. The
>DAC1220 does indeed seem to be the part I was thinking of using, and
>it does offer only 20-bits.
>
>Thanks for the correction.

---
The worm turns?

Refreshing...

JF
From: Steve on 30 Jan 2010 17:27
On Fri, 29 Jan 2010 17:22:24 -0600, John Fields
<jfields(a)austininstruments.com> wrote:

>On Fri, 29 Jan 2010 17:33:44 -0500, Steve <steve(a)nomail.net> wrote:
>
>>Yes, it does seem that digital would be best for me. This design will
>>also be measuring current during the voltage scan using a computer
>>data acquisition card, so a card with a dac could be used to generate
>>the ramp. But the less expensive 16 bit dac cards do not allow their
>>reference and offset voltages to be set externally, so their range is
>>restricted to +/- 10 V which is 0.3 mV lsb. In practice, that may be
>>ok.
>
>I've already posted a digital scheme which will allow you to accomplish
>what you said you wanted to do, but without the constraints you've
>introduced which the "less expensive" DAC cards will place on you.
>
>can you tell us what, exactly, you want to do and how much money you've
>got to be able to do it with, please?

This will be scanning voltage for electrochemical compound research
for battery cycling. Slow scan needed because of slow diffusion in
the materials. University research, so money is an issue. Even
hundreds of dollars cost difference can be an issue. Looking for
in-lab built device(s) instead of spending thousands for a commercial
instrument. 12 bit DAC interface cards are $150, 16 bit are $400.

From: JosephKK on 31 Jan 2010 13:58
On Thu, 28 Jan 2010 21:26:17 -0800 (PST), "miso(a)sushi.com" <miso(a)sushi.com> wrote:

>On Jan 28, 5:46 pm, Joerg <inva...(a)invalid.invalid> wrote:
>> Steve wrote:
>> > I'm looking for a design (analog ?) for a triangle ramp generator with
>> > an adjustable slope around 100 microvolts / sec.  Its output voltage
>> > ramp limits need to be independtly adjustable. The typical range is
>> > 2.0 to 4.8 volts which results in a total period of 15.6 hours.  It
>> > would need to be able to be reset or held at one of its limits (its
>> > lower voltage) and started upon an external signal (relay contact
>> > closure, digital logic state change, etc).   Unipolar positive output
>> > voltage range is fine.
>>
>> Can you use the timer of a uC and PWM a reference that is accurate
>> enough for your purpose? Maybe even the old TL431 suffices :-)
>>
>> Then lowpass it via RC.
>>
>> --
>> Regards, Joerg
>>
>> http://www.analogconsultants.com/
>>
>> "gmail" domain blocked because of excessive spam.
>> Use another domain or send PM.
>
>That would be some significant time constant for the RC filter.

Yep. Even if you used high frequency dither to get a smoother average
slope out of the DAC.
From: JosephKK on 31 Jan 2010 14:20
On Sat, 30 Jan 2010 09:23:10 -0800 (PST), MooseFET <kensmith(a)rahul.net> wrote:

>On Jan 29, 9:27 pm, Paul Keinanen <keina...(a)sci.fi> wrote:
>> On Fri, 29 Jan 2010 06:37:05 -0800 (PST), MooseFET
>>
>>
>>
>> <kensm...(a)rahul.net> wrote:
>> >On Jan 28, 2:43 pm, Steve <st...(a)nomail.net> wrote:
>> >> I'm looking for a design (analog ?) for a triangle ramp generator with
>> >> an adjustable slope around 100 microvolts / sec.  Its output voltage
>> >> ramp limits need to be independtly adjustable. The typical range is
>> >> 2.0 to 4.8 volts which results in a total period of 15.6 hours.  It
>> >> would need to be able to be reset or held at one of its limits (its
>> >> lower voltage) and started upon an external signal (relay contact
>> >> closure, digital logic state change, etc).   Unipolar positive output
>> >> voltage range is fine.
>>
>> >The micros from Silabs have built in DACs.  They are only 12 bits but
>> >that may be all you really need.  You can follow the DAC with a low
>> >pass filter and dither the LSB to make the ramp much smoother.  Since
>> >you can stuff numbers into the DAC at about 100KHz and your output
>> >doesn't have much of a bandwidth the filter can be a very serious low
>> >pass.
>>
>> Apparently these devices use R/2R type  DACs.
>>
>> While in principle a high speed low resolution DAC could be used as a
>> slow speed high resolution DAC by oversampling, the linearity errors
>> could be a problem with such slow ramps.
>
>It depends on whether you need a perfect ramp or only a monotonic rise
>that is good over modest spans.
>
>> While an ideal 12 bit converter would generate a clean step from say
>> 7FF.00 to 800.00, the actual analog step could be 7FF.ff to 800.00 and
>> the device would still considered monotonic :-).
>
>The Silabs ones appear to have a step size that is always within
>about
>1/4 LSB of what it should be.
>
>> At least a quite large (several LSB) dither noise amplitude in the
>> digital domain needs to be added, to get rid of the worst linearity
>> errors. Some RC filtering on the analog side will then remove the
>> dither noise.
>
>The dither can be done at the update frequency of the DAC and it works
>quite well. I have done it. The low pass filter needed to get a good
>signal in the 0-100Hz band is not all that hard to do. The dither
>doesn't need to be random. My code tends to create chaos for the
>points
>that are not rational values. For others it makes a fast cycle of 3
>points.
>
Yes. More interestingly, the dither pattern can include a low value
linear slope component as well. The result is sometimes called noise
shaping.
>
>> >If you get the more "up market" ones, the micro has a fairly accurate
>> >oscillator built in.  This may save you from needing a crystal.
>>
>> On delta/sigma etc. type converters the fluctuation of the clock would
>> alter the output value, thus an oscillator with low phase noise is
>> required and the oscillator should also be free of microphonics,
>> unless the RC filter cut-off would be below 1 Hz, however, such
>> filters would either have a very high output impedance or would
>> require a huge non-electrolytic capacitor.
>
>Doing a cycle of 3 bits on a 12 bit converter means that the timing
>issue starts off 60dB+ down from the full scale. This means that an
>oscillator with jitter in the important band that is 5 digits down
>will do as well as 24bits.
>
>The non-electrolytic capacitors in the filter have to be large but not
>huge.
>
>
> !\
> ----/\/\----+---! >-----------------------+---+-- Output
> ! !/ ! !
> Clarge=== ---/\/\---+---/\/\--- \
> ! ! ! /
> ! /-!- \
> -------+----< ! !
> \+!----------------+
> !
> === Huge but leaky
> !
> GND
>
>You don't get 2 poles worth of noise supression but the leakage in
>the
>huge capacitor doesn't create an offset.
>
>
>> Thus, high quality timing is requiring, so that the analog RC filter
>> would only have to remove oversampling noise, thus operating at a high
>> (100 Hz - 10 kHz) cut-off frequency.
From: John Fields on 31 Jan 2010 21:01
On Sat, 30 Jan 2010 17:27:23 -0500, Steve <steve(a)nomail.net> wrote:

>On Fri, 29 Jan 2010 17:22:24 -0600, John Fields
><jfields(a)austininstruments.com> wrote:
>
>>On Fri, 29 Jan 2010 17:33:44 -0500, Steve <steve(a)nomail.net> wrote:
>>
>>>Yes, it does seem that digital would be best for me. This design will
>>>also be measuring current during the voltage scan using a computer
>>>data acquisition card, so a card with a dac could be used to generate
>>>the ramp. But the less expensive 16 bit dac cards do not allow their
>>>reference and offset voltages to be set externally, so their range is
>>>restricted to +/- 10 V which is 0.3 mV lsb. In practice, that may be
>>>ok.
>>
>>I've already posted a digital scheme which will allow you to accomplish
>>what you said you wanted to do, but without the constraints you've
>>introduced which the "less expensive" DAC cards will place on you.
>>
>>can you tell us what, exactly, you want to do and how much money you've
>>got to be able to do it with, please?
>
>This will be scanning voltage for electrochemical compound research
>for battery cycling. Slow scan needed because of slow diffusion in
>the materials. University research, so money is an issue. Even
>hundreds of dollars cost difference can be an issue. Looking for
>in-lab built device(s) instead of spending thousands for a commercial
>instrument. 12 bit DAC interface cards are $150, 16 bit are $400.

---
Ahhh! In-lab built!

Since you've got in-house test and assembly talent, I'll post a
schematic for you in a day or so that should get you what you need for a
few hundred dollars, probably including PCB fab if you're careful. ;)

JF
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