Prev: Something weird just happened...
Next: inverting dc-dc converter circuit
From: Paul Keinanen on 1 Feb 2010 00:07
On Sun, 31 Jan 2010 13:10:11 -0800, Joerg <invalid(a)invalid.invalid>
wrote:

>>
>> Yep. Even if you used high frequency dither to get a smoother average
>> slope out of the DAC.
>
>
>Who says you can only use one DAC? Use one for coarse and another for
>vernier. Oh, now I've dropped the bag'o tricks and spilled it out :-)

That would be nice, if the coarse DAC would have ideal voltage steps.

While you could use four serial (UART) ports to generate 3 bit PWM
each and after filtering, sum the currents with 512:64:8:1 ratios, I
very much doubt that you would get a monotonic 12 bit response, not at
least without tweaking those resistors on a case by case basis.

From: JosephKK on 1 Feb 2010 01:09
On Sun, 31 Jan 2010 18:18:36 -0800 (PST), George Herold <ggherold(a)gmail.com> wrote:

>On Jan 31, 4:10 pm, Joerg <inva...(a)invalid.invalid> wrote:
>> JosephKK wrote:
>> > On Thu, 28 Jan 2010 21:26:17 -0800 (PST), "m...(a)sushi.com" <m...(a)sushi.com> wrote:
>>
>> >> On Jan 28, 5:46 pm, Joerg <inva...(a)invalid.invalid> wrote:
>> >>> Steve wrote:
>> >>>> I'm looking for a design (analog ?) for a triangle ramp generator with
>> >>>> an adjustable slope around 100 microvolts / sec.  Its output voltage
>> >>>> ramp limits need to be independtly adjustable. The typical range is
>> >>>> 2.0 to 4.8 volts which results in a total period of 15.6 hours.  It
>> >>>> would need to be able to be reset or held at one of its limits (its
>> >>>> lower voltage) and started upon an external signal (relay contact
>> >>>> closure, digital logic state change, etc).   Unipolar positive output
>> >>>> voltage range is fine.
>> >>> Can you use the timer of a uC and PWM a reference that is accurate
>> >>> enough for your purpose? Maybe even the old TL431 suffices :-)
>>
>> >>> Then lowpass it via RC.
>>
>> >>> --
>> >>> Regards, Joerg
>>
>> >>>http://www.analogconsultants.com/
>>
>> >>> "gmail" domain blocked because of excessive spam.
>> >>> Use another domain or send PM.
>> >> That would be some significant time constant for the RC filter.
>>
>> > Yep.  Even if you used high frequency dither to get a smoother average
>> > slope out of the DAC.
>>
>> Who says you can only use one DAC? Use one for coarse and another for
>> vernier. Oh, now I've dropped the bag'o tricks and spilled it out :-)
>>
>> --
>> Regards, Joerg
>>
>> http://www.analogconsultants.com/
>>
>> "gmail" domain blocked because of excessive spam.
>> Use another domain or send PM.- Hide quoted text -
>>
>> - Show quoted text -
>
>Ahh you'll never see this reply, but Thanks Joerg, that sound like a
>nice trick to tuck away.
>
>George H.

I have seen that for A/D and D/A converters since the late 1970s.
I suspect the idea came about from multispeed synchro systems, where
two synchros geared say 36 to 1 were both used to transmit position
information.
Google it up.
From: JosephKK on 1 Feb 2010 01:14
On Sun, 31 Jan 2010 16:39:37 -0800 (PST), MooseFET <kensmith(a)rahul.net> wrote:

>On Jan 31, 11:20 am, "JosephKK"<quiettechb...(a)yahoo.com> wrote:
>> On Sat, 30 Jan 2010 09:23:10 -0800 (PST), MooseFET <kensm...(a)rahul.net> wrote:
>[.. dither on DAC ...]
>> >The dither can be done at the update frequency of the DAC and it works
>> >quite well.  I have done it.  The low pass filter needed to get a good
>> >signal in the 0-100Hz band is not all that hard to do.  The dither
>> >doesn't need to be random. My code tends to create chaos for the
>> >points
>> >that are not rational values.  For others it makes a fast cycle of 3
>> >points.
>>
>> Yes.  More interestingly, the dither pattern can include a low value
>> linear slope component as well.  The result is sometimes called noise
>> shaping.
>
>What I do is keep track of the LSBs below the ones that could be sent
>the the DAC. These get added into the next value before preparing it
>to go to the DAC. This pushes the noise up towards the Nyquist.
>
>The "dither" is a simple -1,0,+1 cycle that is scaled to be just a
>little
>under 3 x LSB. It forces there to be some bits going into the "lost
>bits"
>logic even if the number happens to have all zeros below the point
>where
>it gets cut off for the DAC.
>
It does not have to be that simple.
>>
>>
>>
>> >> >If you get the more "up market" ones, the micro has a fairly accurate
>> >> >oscillator built in.  This may save you from needing a crystal.
>>
>> >> On delta/sigma etc. type converters the fluctuation of the clock would
>> >> alter the output value, thus an oscillator with low phase noise is
>> >> required and the oscillator should also be free of microphonics,
>> >> unless the RC filter cut-off would be below 1 Hz, however, such
>> >> filters would either have a very high output impedance or would
>> >> require a huge non-electrolytic capacitor.
>>
>> >Doing a cycle of 3 bits on a 12 bit converter means that the timing
>> >issue starts off 60dB+ down from the full scale.  This means that an
>> >oscillator with jitter in the important band that is 5 digits down
>> >will do as well as 24bits.
>>
>> >The non-electrolytic capacitors in the filter have to be large but not
>> >huge.
>>
>> >                   !\
>> >   ----/\/\----+---! >-----------------------+---+-- Output
>> >               !   !/                        !   !
>> >        Clarge===       ---/\/\---+---/\/\---    \
>> >               !       !          !              /
>> >               !              /-!-               \
>> >                -------+----<   !                !
>> >                              \+!----------------+
>> >                                                 !
>> >                                                === Huge but leaky
>> >                                                 !
>> >                                                GND
>>
>> >You don't get 2 poles worth of noise supression but the leakage in
>> >the
>> >huge capacitor doesn't create an offset.
>>
>> >> Thus, high quality timing is requiring, so that the analog RC filter
>> >> would only have to remove oversampling noise, thus operating at a high
>> >> (100 Hz - 10 kHz) cut-off frequency.
>>
>>
From: Ban on 2 Feb 2010 02:38

"Steve" <steve(a)nomail.net> schrieb im Newsbeitrag
news:69o6m51n6dmut8krf9ncjag8vlf6fhsnl9(a)4ax.com...
> Yes, it does seem that digital would be best for me. This design will
> also be measuring current during the voltage scan using a computer
> data acquisition card, so a card with a dac could be used to generate
> the ramp. But the less expensive 16 bit dac cards do not allow their
> reference and offset voltages to be set externally, so their range is
> restricted to +/- 10 V which is 0.3 mV lsb. In practice, that may be
> ok.
>

If you want to use a 16-bit D/A-card you can scale down the output to
100uV/step and filter it, so you get a smooth ramp. There will be a delay of
4s on the ramp an when it stops the last 250uV will settle assymptotically.
The opamp is a precision part and is stablr with any capacitive load. It can
source or sink up to 20mA and can be supplied by the reference Voltage, if
your 2nd channel on the D/A.card can output that much. otherwise use a
separate supply and take only the 10V reference voltage from that channel.
If you have the option of unipolar output, no reference voltage is needed.
The lowest reachable voltage with 100k load is +10mV, with 1k +600mV, if
that is too much you also will need a negative supply for the opamp. If you
need more output current, you can add a buffer like LT1010 (inside the
fb-loop)
Vrefo+10V
|
o----------------.
| |
.-. |
| | |
| |20k |
-10V...+10V '-' |
___ | |\|
DAC-IN o-|___|--o-o----o-------|+\
20k | | | >---o--o
| |220u .-|-/ |
.-. |+ | |/| |
| | === | | |
19k014| | /-\ | === |
'-' | | GND |
| | '--------'
=== === LTC1152
GND GND
(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)

ciao Ban


From: John Fields on 3 Feb 2010 14:32
On Sun, 31 Jan 2010 20:01:27 -0600, John Fields
<jfields(a)austininstruments.com> wrote:

>On Sat, 30 Jan 2010 17:27:23 -0500, Steve <steve(a)nomail.net> wrote:
>
>>On Fri, 29 Jan 2010 17:22:24 -0600, John Fields
>><jfields(a)austininstruments.com> wrote:
>>
>>>On Fri, 29 Jan 2010 17:33:44 -0500, Steve <steve(a)nomail.net> wrote:
>>>
>>>>Yes, it does seem that digital would be best for me. This design will
>>>>also be measuring current during the voltage scan using a computer
>>>>data acquisition card, so a card with a dac could be used to generate
>>>>the ramp. But the less expensive 16 bit dac cards do not allow their
>>>>reference and offset voltages to be set externally, so their range is
>>>>restricted to +/- 10 V which is 0.3 mV lsb. In practice, that may be
>>>>ok.
>>>
>>>I've already posted a digital scheme which will allow you to accomplish
>>>what you said you wanted to do, but without the constraints you've
>>>introduced which the "less expensive" DAC cards will place on you.
>>>
>>>can you tell us what, exactly, you want to do and how much money you've
>>>got to be able to do it with, please?
>>
>>This will be scanning voltage for electrochemical compound research
>>for battery cycling. Slow scan needed because of slow diffusion in
>>the materials. University research, so money is an issue. Even
>>hundreds of dollars cost difference can be an issue. Looking for
>>in-lab built device(s) instead of spending thousands for a commercial
>>instrument. 12 bit DAC interface cards are $150, 16 bit are $400.
>
>---
>Ahhh! In-lab built!
>
>Since you've got in-house test and assembly talent, I'll post a
>schematic for you in a day or so that should get you what you need for a
>few hundred dollars, probably including PCB fab if you're careful. ;)

---
Steve,

"A day or so" has stretched to the beginning of next week, sorry... :(

BTW, how much free I.O. do you have available?

JF
First  |  Prev  |  Next  |  Last
Pages: 1 2 3 4
Prev: Something weird just happened...
Next: inverting dc-dc converter circuit