Prev: How to find latches in Xilinx ISE 10.1
Next: Nios Memory Protection Unit
From: Eric Chomko on 12 Apr 2010 13:47
I am working with a Virtex-5 FPGA PCIe-based board and want to create
three interfaces (lanes?). One that is a two way serial interface
running at 1 MHz. Another running at 1 MHz but only input to the
board. The last interface or lane will be 16 bit input only running
at 28 MHz. I am reviewing the Avnet Development Kit User Guide for
the board and have the Integrated Endpoint Block for PCI Express
Designs document. I suspect all the answers how to configure the
board are in those documents but since I have never done this before,
I don't know where to start. Also, the FPGA code will be taken from
another system that has a 1 MHz serial I/O, 1 MHz serial input-only,
and a 28 MHz 16 bit parallel, input-only custom interfaces. The PCIe
bus in this case will emulate those three.

Any suggestions from anyone with more experience? I really appreciate
anything I can get about this.

Thanks,
Eric
From: john.orlando on 12 Apr 2010 22:06
On Apr 12, 12:47 pm, Eric Chomko <pne.cho...(a)comcast.net> wrote:
> I am working with a Virtex-5 FPGA PCIe-based board and want to create
> three interfaces (lanes?).  One that is a two way serial interface
> running at 1 MHz.  Another running at 1 MHz but only input to the
> board.  The last interface or lane will be 16 bit input only running
> at 28 MHz.  
<snip>

From the sounds of your post, I think your best bet would be to first
start be getting a better handle on PCIe and how it works in general.
Spending a few days reading through Mindshare's PCIe System
Architecture book will probably help explain the general topology of
PCIe. Once the fundamentals of PCIe are understood, it will make
mapping these to an FPGA implementation much easier.

Here is Amazon's link to the book:

http://www.amazon.com/Express-System-Architecture-Mindshare-Inc/dp/0321156307

The Mindshare books are a goldmine, IMHO.

Good luck,

John
From: Eric Chomko on 13 Apr 2010 18:20
On Apr 12, 10:06 pm, "john.orla...(a)gmail.com" <john.orla...(a)gmail.com>
wrote:
> On Apr 12, 12:47 pm, Eric Chomko <pne.cho...(a)comcast.net> wrote:> I am working with a Virtex-5 FPGA PCIe-based board and want to create
> > three interfaces (lanes?).  One that is a two way serial interface
> > running at 1 MHz.  Another running at 1 MHz but only input to the
> > board.  The last interface or lane will be 16 bit input only running
> > at 28 MHz.  
>
> <snip>
>
> From the sounds of your post, I think your best bet would be to first
> start be getting a better handle on PCIe and how it works in general.
> Spending a few days reading through Mindshare's PCIe System
> Architecture book will probably help explain the general topology of
> PCIe.  Once the fundamentals of PCIe are understood, it will make
> mapping these to an FPGA implementation much easier.
>
> Here is Amazon's link to the book:
>
> http://www.amazon.com/Express-System-Architecture-Mindshare-Inc/dp/03...
>
> The Mindshare books are a goldmine, IMHO.
>
> Good luck,
>
> John

Thanks for the advice I will take it!

Eric
From: haydin on 20 Apr 2010 05:07
Eric,

I would also recommend the following resources:

1) Read the PCI Express specification, if you can get access to it:
http://www.pcisig.com/specifications/pciexpress/specifications/
2) Intel Press has a very good book on PCI Express:
http://www.intel.com/intelpress/sum_pciexpress.htm

Hakan

Linera - http://www.linera.com.tr
 | 
Pages: 1
Prev: How to find latches in Xilinx ISE 10.1
Next: Nios Memory Protection Unit