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From: lonny on 13 Jan 2010 18:39
using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need
the terminations
at the end of the fly-by routing of the address bus?



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From: Adam Górski on 14 Jan 2010 05:52
lonny pisze:
> using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need
> the terminations
> at the end of the fly-by routing of the address bus?
>
>
>
> ---------------------------------------
> This message was sent using the comp.arch.fpga web interface on
> http://www.FPGARelated.com

DDR3 has got not only max frequency. See min frequency or min tck.

Adam
From: Nico Coesel on 14 Jan 2010 13:20
=?ISO-8859-2?Q?Adam_G=F3rski?= <totutousungorskia(a)malpawp.pl> wrote:

>lonny pisze:
>> using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need
>> the terminations
>> at the end of the fly-by routing of the address bus?

Probably not.

>>
>>
>> ---------------------------------------
>> This message was sent using the comp.arch.fpga web interface on
>> http://www.FPGARelated.com
>
>DDR3 has got not only max frequency. See min frequency or min tck.

AFAIK only the PLL has a minimum frequency. In order to detect and
configure the memory you have to run it at a lower frequency which
implies DDR3 memory can also be used at (poorly specified) lower
frequencies.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: Sean Durkin on 14 Jan 2010 13:31
Adam G�rski wrote:
> lonny pisze:
>> using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you
>> need
>> the terminations
>> at the end of the fly-by routing of the address bus?
>
> DDR3 has got not only max frequency. See min frequency or min tck.

He has the DLL disabled, which is the only component that actually has
the minimum frequency restriction. If you disable the DLL, the phase
relationship between input clock and output data strobe and data is not
fixed and specified, but at 50MHz that might not be a problem.

But the DRAM manufacturers usually don't specify or guarantee anything
when you run the chips in that mode, so I've never used it...

As to the OP's question: It depends... On your stackup, the length of
the routes, the number of chips hanging on the address bus... It's not
just the frequency that matters. It would be best to simulate the
transmission lines beforehand.

HTH,
Sean
From: Adam Górski on 15 Jan 2010 07:24

>>> using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need
>>> the terminations
>>> at the end of the fly-by routing of the address bus?
>> DDR3 has got not only max frequency. See min frequency or min tck.
>
> AFAIK only the PLL has a minimum frequency. In order to detect and
> configure the memory you have to run it at a lower frequency which
> implies DDR3 memory can also be used at (poorly specified) lower
> frequencies.
>

For me if I see tck min in datasheet it means it has min tck.
You can't relay on "maybe".

Adam
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