What is happening to Atmel EEPROMs?
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From: Ulf Samuelsson on 26 Mar 2010 19:39 Leon skrev: > On 25 Mar, 11:20, Peter <nos...(a)nospam9876.com> wrote: >> They have doubled their prices and the lead times are 18 weeks. >> >> Yet, others are making them OK. >> >> Are Atmel trying to get out of the business? >> x----------x > > They got rid of their fabs, and are now having to join the queue at > TSMC or wherever they get their chips made. They are probably having > to pay a lot more for them, because of demand for the manufacturing > facilities. Microchip have their own fabs, and seem able to keep up > with demand. While at least some memory chips are outsourced, the AVRs are still manufactured inside Atmel. I get leadtime guides from distributors and many semiconductor companies have 20+ weeks leadtime right now. Talked to one large customer who got 42 weeks lead time for mobile DDRs. When lead times go up, some customers tend to order components from several suppliers, so apparent demand is higher than real demand, so anything in stock is swallowed up immediately. If there is no stock, then it normally takes 16 weeks to produce new things for any semiconductor manufacturer. Quite often, the fab capacity is not the problem, but testing is. If you can't buy new testers, then capacity cannot increase. Companies doing test equipment cant deliver, because they have long lead times on components. Hmmm... Best Regards Ulf Samuelsson
From: Ulf Samuelsson on 26 Mar 2010 19:40 Peter skrev: > Leon <leon355(a)btinternet.com> wrote: > >> On 25 Mar, 11:20, Peter <nos...(a)nospam9876.com> wrote: >>> They have doubled their prices and the lead times are 18 weeks. >>> >>> Yet, others are making them OK. >>> >>> Are Atmel trying to get out of the business? >>> x----------x >> They got rid of their fabs, and are now having to join the queue at >> TSMC or wherever they get their chips made. They are probably having >> to pay a lot more for them, because of demand for the manufacturing >> facilities. Microchip have their own fabs, and seem able to keep up >> with demand. > > Not a good reason to design-in an Atmel processor then... I have one > running in production volumes but need to update it, and another was > going to go in to replace a Hitachi uC. We were going to use the > ATmega 128L. > > x----------x ATmega128A is probably a better choice. BR Ulf Samuelsson
From: Ulf Samuelsson on 26 Mar 2010 20:02 TheM skrev: > "Nico Coesel" <nico(a)puntnl.niks> wrote in message news:4bacf169.1721173156(a)news.planet.nl... >> "TheM" <DontNeedSpam(a)test.com> wrote: >> >>> "Spehro Pefhany" <speffSNIP(a)interlogDOTyou.knowwhat> wrote in message news:5elnq5d2ncjvs91v1cu5dmt5tbntuhefg3(a)4ax.com... >>>> On Thu, 25 Mar 2010 13:19:46 -0800, "Bob Eld" <nsmontassoc(a)yahoo.com> >>>> wrote: >>>> >>>>> "Peter" <nospam(a)nospam9876.com> wrote in message >>>>> news:9lhmq5plg1gr3sduo9n52mdi5g6iiqucqc(a)4ax.com... >>>>>> They have doubled their prices and the lead times are 18 weeks. >>> Is this limited to EEPROM/Memory only or uCPU as well? >>> >>> Definitely worth considering getting out of AVR. >>> Do NPX ARM come with on-chip FLASH? >> Yes, all of them have 128 bit wide flash that allows zero waitstate >> execution at the maximum CPU clock. > > Not bad, I ordered a couple books on ARM off Amazon, may get into it finally. > From what I see they are same price as AVR mega, low power and much faster. > And NXP is very generous with samples. > > M > > The typical 32 bitters of today are implemented using advanced flash technologies which allows high density memories in small chip areas, but they are not low power. The inherent properties of the process makes for high leakage. When you see power consumption in sleep of around 1-2 uA, this is when the chip is turned OFF. Only a small part of the chip is powered, RTC and a few other things. When you implement in a 0.25u process or higher, you can have the chip fully initialized and ready to react on input while using 1-2 uA in sleep. That is a big difference. While the NXP devices gets zero waitstate from 128 bit bus, this also makes them extremely power hungry. An LPC ARM7 uses about 2 x the current of a SAM7. It gets higher performance in ARM mode. The ARM mode has a price in code size, so if you want more features, then you better run in Thumb mode. The SAM7 with 32 bit flash is actually faster than the LPC when running in Thumb mode, (at the same frequency) since the SAM7 uses as 33 MHz flash, while the LPC uses a 24 Mhz flash. In thumb mode, the 32 bit access gives you two instructions per cycle so in average this gives you 1 instruction per clock on the SAM7. Less waitstates means higher performance. By copying a few 32 bit ARM routines to SRAM, you can overcome that limitation. You can get slightly higher top frequency out of the LPC, but that again increases the power consumption. For Cortex-M3 I did some test on the new SAM3, which can be configured to use both 64 bit or 128 bit memories. With a 128 bit memory, you can wring about 5% extra performance out of the chip compared to 64 bit operation. From a power consumption point of view it is probably better to increase the clock frequency by 5% than to enable the 128 bit mode. It is therefore only the most demanding applications that have any use for the 128 bit memory. Testing on other Cortex-M3 chips indicate similar results. Someone told me that they tried executing out of SRAM on an STM32 and this was actually slower than executing out of flash. Executing out of external memory also appears to be a problem, since there is no cache/burst and bandwidth seems to be lower than equivalent ARM7 devices. Current guess is that the AHB bus has some delays due to synchronization. Also if you execute out of SRAM you are going to have conflicts with data access. Something which is avoided when you execute out of flash. Would be curious to hear about other peoples experience about this. Best Regards Ulf Samuelsson
From: langwadt on 26 Mar 2010 20:27 On 27 Mar., 01:02, Ulf Samuelsson <u...(a)a-t-m-e-l.com> wrote: > TheM skrev: > > > > > "Nico Coesel" <n...(a)puntnl.niks> wrote in messagenews:4bacf169.1721173156(a)news.planet.nl... > >> "TheM" <DontNeedS...(a)test.com> wrote: > > >>> "Spehro Pefhany" <speffS...(a)interlogDOTyou.knowwhat> wrote in messagenews:5elnq5d2ncjvs91v1cu5dmt5tbntuhefg3(a)4ax.com... > >>>> On Thu, 25 Mar 2010 13:19:46 -0800, "Bob Eld" <nsmontas...(a)yahoo.com> > >>>> wrote: > > >>>>> "Peter" <nos...(a)nospam9876.com> wrote in message > >>>>>news:9lhmq5plg1gr3sduo9n52mdi5g6iiqucqc(a)4ax.com... > >>>>>> They have doubled their prices and the lead times are 18 weeks. > >>> Is this limited to EEPROM/Memory only or uCPU as well? > > >>> Definitely worth considering getting out of AVR. > >>> Do NPX ARM come with on-chip FLASH? > >> Yes, all of them have 128 bit wide flash that allows zero waitstate > >> execution at the maximum CPU clock. > > > Not bad, I ordered a couple books on ARM off Amazon, may get into it finally. > > From what I see they are same price as AVR mega, low power and much faster. > > And NXP is very generous with samples. > > > M > > The typical 32 bitters of today are implemented using advanced > flash technologies which allows high density memories in small chip > areas, but they are not low power. > > The inherent properties of the process makes for high leakage. > When you see power consumption in sleep of around 1-2 uA, > this is when the chip is turned OFF. > Only a small part of the chip is powered, RTC and a few other things. > > When you implement in a 0.25u process or higher, you can have the chip > fully initialized and ready to react on input while using > 1-2 uA in sleep. > > That is a big difference. > > While the NXP devices gets zero waitstate from 128 bit bus, > this also makes them extremely power hungry. > An LPC ARM7 uses about 2 x the current of a SAM7. > It gets higher performance in ARM mode. > > The ARM mode has a price in code size, so if you want more features, > then you better run in Thumb mode. The SAM7 with 32 bit flash is > actually faster than the LPC when running in Thumb mode, > (at the same frequency) since the SAM7 uses as 33 MHz flash, > while the LPC uses a 24 Mhz flash. > In thumb mode, the 32 bit access gives you two instructions > per cycle so in average this gives you 1 instruction per clock on the SAM7. > how does that make any sense? wheter an instruction is 16 or 32bit, 24MHz * 128bit is still more that 33MHz * 32 bit ... snip > > Best Regards > Ulf Samuelsson -Lasse
From: Ulf Samuelsson on 27 Mar 2010 03:15
langwadt(a)fonz.dk skrev: > On 27 Mar., 01:02, Ulf Samuelsson <u...(a)a-t-m-e-l.com> wrote: >> TheM skrev: >> >> >> >>> "Nico Coesel" <n...(a)puntnl.niks> wrote in messagenews:4bacf169.1721173156(a)news.planet.nl... >>>> "TheM" <DontNeedS...(a)test.com> wrote: >>>>> "Spehro Pefhany" <speffS...(a)interlogDOTyou.knowwhat> wrote in messagenews:5elnq5d2ncjvs91v1cu5dmt5tbntuhefg3(a)4ax.com... >>>>>> On Thu, 25 Mar 2010 13:19:46 -0800, "Bob Eld" <nsmontas...(a)yahoo.com> >>>>>> wrote: >>>>>>> "Peter" <nos...(a)nospam9876.com> wrote in message >>>>>>> news:9lhmq5plg1gr3sduo9n52mdi5g6iiqucqc(a)4ax.com... >>>>>>>> They have doubled their prices and the lead times are 18 weeks. >>>>> Is this limited to EEPROM/Memory only or uCPU as well? >>>>> Definitely worth considering getting out of AVR. >>>>> Do NPX ARM come with on-chip FLASH? >>>> Yes, all of them have 128 bit wide flash that allows zero waitstate >>>> execution at the maximum CPU clock. >>> Not bad, I ordered a couple books on ARM off Amazon, may get into it finally. >>> From what I see they are same price as AVR mega, low power and much faster. >>> And NXP is very generous with samples. >>> M >> The typical 32 bitters of today are implemented using advanced >> flash technologies which allows high density memories in small chip >> areas, but they are not low power. >> >> The inherent properties of the process makes for high leakage. >> When you see power consumption in sleep of around 1-2 uA, >> this is when the chip is turned OFF. >> Only a small part of the chip is powered, RTC and a few other things. >> >> When you implement in a 0.25u process or higher, you can have the chip >> fully initialized and ready to react on input while using >> 1-2 uA in sleep. >> >> That is a big difference. >> >> While the NXP devices gets zero waitstate from 128 bit bus, >> this also makes them extremely power hungry. >> An LPC ARM7 uses about 2 x the current of a SAM7. >> It gets higher performance in ARM mode. >> >> The ARM mode has a price in code size, so if you want more features, >> then you better run in Thumb mode. The SAM7 with 32 bit flash is >> actually faster than the LPC when running in Thumb mode, >> (at the same frequency) since the SAM7 uses as 33 MHz flash, >> while the LPC uses a 24 Mhz flash. >> In thumb mode, the 32 bit access gives you two instructions >> per cycle so in average this gives you 1 instruction per clock on the SAM7. >> > > how does that make any sense? wheter an instruction is 16 or 32bit, > 24MHz * 128bit is still more that 33MHz * 32 bit ... > When you run in Thumb mode and 1 waitstate, all instructions are 16 bit and the SAM7 memory controller fetches 32 bit so and with prefetch, there should always be zero waitstates for sequential fetch. For Thumb mode, you have several cases depending on processor speed. Figures are for (non-sequential/sequential) access. LPC SAM7 < 24 MHz: 0/0 0/0 same speed 24-33 MHz: 1/0 0/0 (SAM7 faster) 33-48 MHz: 1/0 1/0 same speed 48-66 MHz 2/0 1/0 (SAM7 faster) so the LPC2xxx has to run at higher clock frequencies to meet the SAM7S performance. The 128 bit memory is overkill for thumb mode and just wastes power. You really need to run ARM mode for the 128 bit memory to make sense. You can try overclocking the SAM7S if you are not running over the full temp range. 48 MHz zero waitstates seems to work OK, but not up to +85'C. > snip > >> Best Regards >> Ulf Samuelsson > > -Lasse |