What is happening to Atmel EEPROMs?
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From: JosephKK on 28 Mar 2010 19:06 On Fri, 26 Mar 2010 17:27:16 -0700 (PDT), "langwadt(a)fonz.dk" <langwadt(a)fonz.dk> wrote: >On 27 Mar., 01:02, Ulf Samuelsson <u...(a)a-t-m-e-l.com> wrote: >> TheM skrev: >> >> >> >> > "Nico Coesel" <n...(a)puntnl.niks> wrote in messagenews:4bacf169.1721173156(a)news.planet.nl... >> >> "TheM" <DontNeedS...(a)test.com> wrote: >> >> >>> "Spehro Pefhany" <speffS...(a)interlogDOTyou.knowwhat> wrote in messagenews:5elnq5d2ncjvs91v1cu5dmt5tbntuhefg3(a)4ax.com... >> >>>> On Thu, 25 Mar 2010 13:19:46 -0800, "Bob Eld" <nsmontas...(a)yahoo.com> >> >>>> wrote: >> >> >>>>> "Peter" <nos...(a)nospam9876.com> wrote in message >> >>>>>news:9lhmq5plg1gr3sduo9n52mdi5g6iiqucqc(a)4ax.com... >> >>>>>> They have doubled their prices and the lead times are 18 weeks. >> >>> Is this limited to EEPROM/Memory only or uCPU as well? >> >> >>> Definitely worth considering getting out of AVR. >> >>> Do NPX ARM come with on-chip FLASH? >> >> Yes, all of them have 128 bit wide flash that allows zero waitstate >> >> execution at the maximum CPU clock. >> >> > Not bad, I ordered a couple books on ARM off Amazon, may get into it finally. >> > From what I see they are same price as AVR mega, low power and much faster. >> > And NXP is very generous with samples. >> >> > M >> >> The typical 32 bitters of today are implemented using advanced >> flash technologies which allows high density memories in small chip >> areas, but they are not low power. >> >> The inherent properties of the process makes for high leakage. >> When you see power consumption in sleep of around 1-2 uA, >> this is when the chip is turned OFF. >> Only a small part of the chip is powered, RTC and a few other things. >> >> When you implement in a 0.25u process or higher, you can have the chip >> fully initialized and ready to react on input while using >> 1-2 uA in sleep. >> >> That is a big difference. >> >> While the NXP devices gets zero waitstate from 128 bit bus, >> this also makes them extremely power hungry. >> An LPC ARM7 uses about 2 x the current of a SAM7. >> It gets higher performance in ARM mode. >> >> The ARM mode has a price in code size, so if you want more features, >> then you better run in Thumb mode. The SAM7 with 32 bit flash is >> actually faster than the LPC when running in Thumb mode, >> (at the same frequency) since the SAM7 uses as 33 MHz flash, >> while the LPC uses a 24 Mhz flash. >> In thumb mode, the 32 bit access gives you two instructions >> per cycle so in average this gives you 1 instruction per clock on the SAM7. >> > >how does that make any sense? wheter an instruction is 16 or 32bit, >24MHz * 128bit is still more that 33MHz * 32 bit ... > >snip > >> >> Best Regards >> Ulf Samuelsson > >-Lasse It all starts with Amdahl's Law. Double the speed of one thing and if none of the rest of the system can use the speed increase you get nothing. (slightly overstated)
From: Jon Kirwan on 28 Mar 2010 19:29 On Sun, 28 Mar 2010 16:06:04 -0700, "JosephKK"<quiettechblue(a)yahoo.com> wrote: ><snip> >It all starts with Amdahl's Law. Double the speed of one thing and if none >of the rest of the system can use the speed increase you get nothing. >(slightly overstated) Sounds like the famous "weakest link" phrase, "A chain is no stronger than its weakest link," which apparently traces back to the English clergyman Charles Kingley's letter, dated December 1, 1856, where he wrote "The devil is very busy, and no one knows better than he, that 'nothing is stronger than its weakest part.'" Others have also written similarly, since. See very near the bottom of page 433 here, for example: http://www.archive.org/stream/workslife10bageuoft#page/432/mode/2up I guess we can add Amdahl to a long list of many stating the exact same thing in slightly different words. Jon
From: krw on 28 Mar 2010 20:22 On Sun, 28 Mar 2010 16:29:21 -0700, Jon Kirwan <jonk(a)infinitefactors.org> wrote: >On Sun, 28 Mar 2010 16:06:04 -0700, >"JosephKK"<quiettechblue(a)yahoo.com> wrote: > >><snip> >>It all starts with Amdahl's Law. Double the speed of one thing and if none >>of the rest of the system can use the speed increase you get nothing. >>(slightly overstated) > >Sounds like the famous "weakest link" phrase, "A chain is no >stronger than its weakest link," which apparently traces back >to the English clergyman Charles Kingley's letter, dated >December 1, 1856, where he wrote "The devil is very busy, and >no one knows better than he, that 'nothing is stronger than >its weakest part.'" > >Others have also written similarly, since. See very near the >bottom of page 433 here, for example: >http://www.archive.org/stream/workslife10bageuoft#page/432/mode/2up > >I guess we can add Amdahl to a long list of many stating the >exact same thing in slightly different words. Ahmdahl's Law is more quantitative than that: http://www.search.com/reference/Amdahl%27s_law
From: Jon Kirwan on 28 Mar 2010 22:04 On Sun, 28 Mar 2010 19:22:10 -0500, "krw(a)att.bizzzzzzzzzzzz" <krw(a)att.bizzzzzzzzzzzz> wrote: >On Sun, 28 Mar 2010 16:29:21 -0700, Jon Kirwan <jonk(a)infinitefactors.org> >wrote: > >>On Sun, 28 Mar 2010 16:06:04 -0700, >>"JosephKK"<quiettechblue(a)yahoo.com> wrote: >> >>><snip> >>>It all starts with Amdahl's Law. Double the speed of one thing and if none >>>of the rest of the system can use the speed increase you get nothing. >>>(slightly overstated) >> >>Sounds like the famous "weakest link" phrase, "A chain is no >>stronger than its weakest link," which apparently traces back >>to the English clergyman Charles Kingley's letter, dated >>December 1, 1856, where he wrote "The devil is very busy, and >>no one knows better than he, that 'nothing is stronger than >>its weakest part.'" >> >>Others have also written similarly, since. See very near the >>bottom of page 433 here, for example: >>http://www.archive.org/stream/workslife10bageuoft#page/432/mode/2up >> >>I guess we can add Amdahl to a long list of many stating the >>exact same thing in slightly different words. > >Ahmdahl's Law is more quantitative than that: >http://www.search.com/reference/Amdahl%27s_law Nice! Jon
From: Anders.Montonen on 29 Mar 2010 06:57
In comp.arch.embedded Nico Coesel <nico(a)puntnl.niks> wrote: > "TheM" <DontNeedSpam(a)test.com> wrote: >>Do NPX ARM come with on-chip FLASH? > Yes, all of them have 128 bit wide flash that allows zero waitstate > execution at the maximum CPU clock. The LP17xx series require flash wait states when run at speeds over 20 MHz. When running at full speed four wait states must be inserted (see the description of the FLASHCFG register, p. 71 in the user manual). The chips do have a flash accelerator (a tiny, simple cache really) to help hide the latency. -a |