Which is the most beautiful and memorable hardware structure in a CPU?
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From: nmm1 on 30 Mar 2010 05:38 In article <27ebdb37-e3ba-4559-be7d-d7f3b6613d77(a)30g2000yqi.googlegroups.com>, MitchAlsup <MitchAlsup(a)aol.com> wrote: >The most memorable hardware structure is the vector indirect >addressing mode. Yes. There were and are more bizarre ones, but they are Not Memorable (see Sellars and Yeatman). Regards, Nick Maclaren.
From: Jonathan Bromley on 30 Mar 2010 08:45 On Mar 30, 10:38 am, n...(a)cam.ac.uk wrote: > Yes. There were and are more bizarre ones, but they are Not Memorable > (see Sellars and Yeatman). Ooooh, I like that. Always good to bring a bit of high culture into the discussion. It may be Memorable, hut was it a Good Thing? _Sellar_ and Yeatman, I think you'll find (without the trailing 's'). Thanks for tickling a long-dormant and much cherished memory. -- Jonathan Bromley
From: Weng Tianxiang on 30 Mar 2010 14:19 On Mar 30, 10:41 am, Jason Zheng <Xin.Zh...(a)jpl.nasa.gov> wrote: > On Sun, 28 Mar 2010 19:06:23 -0700 (PDT) > > Weng Tianxiang <wtx...(a)gmail.com> wrote: > > <snip> > > > And it is strange enough that after PC was created, no big new > > structure in CPU has ever invented. MESI protocol? No. Changing 1 core > > to 2 core, or even 8 cores is considered as a big invention? No. > > My favorite is the Translation Look-aside Buffers (TLB), of course > invented by the IBM engineers. You have to appreciate the way it sounds > (and its irrelevance to its true purpose). Haha, some people don't appreciate stack segment and stack pointer. There two reasons I appreciate most: 1. It is very simple; 2. I handles all subroutine calls with prefect beauty for last 60 years. 3 years ago when I first read BW transform, I was in awe in such a way that made me to excitement for a week. But sadly I found that BW transform cannot get the high compression rate even though we don't pay attention on the time the transform needs. I joined compression group and found there were few discussions on the BW transform, the main reason is its not highest compression rate. Weng
From: Rob Warnock on 30 Mar 2010 21:41 MitchAlsup <MitchAlsup(a)aol.com> wrote: +--------------- | The most memorable hardware structure is the vector indirect | addressing mode. +--------------- I was always rather fond of the PDP-10's multi-level indirect addressing which allowed additional indexing with a different accumulator at each level of indirection, and how that permitted multi-dimension array indexing to be done in a *single* instruction, albeit requiring auxiliary Iliffe vectors for the arrays [as was done in ALGOL-10]. Quoting myself: Newsgroups: alt.folklore.computers Date: Sun, 30 Aug 2009 06:03:04 -0500 From: rpw3(a)rpw3.org (Rob Warnock) Subject: Re: PDP-10 Assembly Language Questions Message-ID: <HrWdnRhVz531wQfXnZ2dnUVZ_v6dnZ2d(a)speakeasy.net> ... For, say, a three-dimensional array, if A, B, & C were already in the proper registers, then "FOO[A,B,C] := FOO[A,B,C] + 1" could be done in *one* instruction!! (No joke!) What, you don't believe me? ;-} Here's the code: MOVE T1,A ; Load up the array indices MOVE T2,B MOVE T3,C AOS @FOO(T1) ; Increment FOO[A,B,C] (and don't skip). [Assumes the first level of Iliffe vectors has the indirect-addressing bit on and "T2" in the index field, and the second level of Iliffe vectors has the indirect-addressing bit *off* and "T3" in the index field.] -Rob ----- Rob Warnock <rpw3(a)rpw3.org> 627 26th Avenue <URL:http://rpw3.org/> San Mateo, CA 94403 (650)572-2607
From: James Harris on 31 Mar 2010 01:48
On 29 Mar, 22:36, Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> wrote: .... > No? Don't like that? OK, the Transputer's tiny 3-register > evaluation stack, with context switches permitted only at > points where the stack is known to be empty. The > 21st century operating system wonks could REALLY learn > something about lightweight elegance from that one. And from its one-byte instructions. Four-bit opcode and four-bit data fields lead to 29 of the most-used instructions taking just one byte and allowing for about 256 others to be encoded in two bytes (though some used more). All this made effective on a 32-bit machine in the 1980s! Of course the stack and zero-operand addressing made such tiny encoding possible. These days a single stack would probably effect a dependency between instructions which did not need one. Perhaps today such would be built as many micro-cores. James |