Which uController to learn?
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From: Spehro Pefhany on 17 Mar 2007 19:23 On Sat, 17 Mar 2007 15:40:48 -0400, the renowned krw <krw(a)att.bizzzz> wrote: >In article <1174153886.787617.256830(a)e1g2000hsg.googlegroups.com>, >mpmillard(a)aol.com says... >> On Mar 15, 8:31?pm, "Anthony Fremont" <spam-...(a)nowhere.com> wrote: >> > usually implement the SFRs the same way... >> >> The differences are minor. >> And if you code properly, its very easy to adjust any relocated SRF's >> that affect program execution. > >Yes, I always wrote a module for each UC that had the names of all >SRFs for that model. This module was then included in the MAKE based >on version. Never, EVER, use absolute addresses for SRFs. > >> Ditto for the Interrupt vectors, which for the "Standard" interrupts >> like T0, T1, etc... are usually at the expected addresses anyway. > >Sure, I hard-coded these at each location, whether they were used or >not. The main source module would have a stub to each ISR. > >> Now, clock cycle / instruction cycle time is another story. >> I think the original 8051 would execute 1 instruction every 12 clocks. >> (?) >> Newer ones can do it in 2. (in other words, a 6x improvement). > >Yes, as I recently found out (duh!) the original 8051 has a bit- >serial ALU. BTW, MUL and DIV are 24 clocks per instruction. How would do you do an 8 x 8 multiply with 24 clocks and a serial ALU? Seems to me you'd need at least 64 clocks. Anyway, MUL and DIV take 4 machine cycles (24 states, 48 oscillator clocks in the original 8x51). Still not 64 unless you're using both clock edges. There is at least one 8-bit micro that is serial internally- the ST-6 (it's a feature they say, lower noise)-- but I am not convinced that the 8051 is. Any cites? Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff(a)interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
From: krw on 17 Mar 2007 21:14 In article <61sov29psuqj3t2jdcd7sdqanli46esjao(a)4ax.com>, speffSNIP(a)interlogDOTyou.knowwhat says... > On Sat, 17 Mar 2007 15:40:48 -0400, the renowned krw <krw(a)att.bizzzz> > wrote: > > >In article <1174153886.787617.256830(a)e1g2000hsg.googlegroups.com>, > >mpmillard(a)aol.com says... > >> On Mar 15, 8:31?pm, "Anthony Fremont" <spam-...(a)nowhere.com> wrote: > >> > usually implement the SFRs the same way... > >> > >> The differences are minor. > >> And if you code properly, its very easy to adjust any relocated SRF's > >> that affect program execution. > > > >Yes, I always wrote a module for each UC that had the names of all > >SRFs for that model. This module was then included in the MAKE based > >on version. Never, EVER, use absolute addresses for SRFs. > > > >> Ditto for the Interrupt vectors, which for the "Standard" interrupts > >> like T0, T1, etc... are usually at the expected addresses anyway. > > > >Sure, I hard-coded these at each location, whether they were used or > >not. The main source module would have a stub to each ISR. > > > >> Now, clock cycle / instruction cycle time is another story. > >> I think the original 8051 would execute 1 instruction every 12 clocks. > >> (?) > >> Newer ones can do it in 2. (in other words, a 6x improvement). > > > >Yes, as I recently found out (duh!) the original 8051 has a bit- > >serial ALU. BTW, MUL and DIV are 24 clocks per instruction. > > How would do you do an 8 x 8 multiply with 24 clocks and a serial ALU? > Seems to me you'd need at least 64 clocks. I don't have the microarchitecture of the original 8051, but you don't need a clock for each bit. The diagonals should be enough. > Anyway, MUL and DIV take 4 machine cycles (24 states, 48 oscillator > clocks in the original 8x51). Still not 64 unless you're using both > clock edges. I thought it was six clocks per machine cycle and two (most) or four (MUL/DIV) cycles per instruction. It's been a long time since I used one though so may be misremembering the convoluted details. > > There is at least one 8-bit micro that is serial internally- the ST-6 > (it's a feature they say, lower noise)-- but I am not convinced that > the 8051 is. Any cites? It was brought up in AFC in the past week or so. I'll see if I can find the reference. -- Keith
From: Mike on 17 Mar 2007 23:39 In article <0001HW.C220350A0041BFCBF01826C8(a)news.sf.sbcglobal.net>, incognito(a)yahoo.com says... > >> Actually, just about anything that has a stack-oriented architecture, or >> a register-oriented architecture with an orthogonal instruction set and >> decent indexing. > >Being a beginner in all this, I have no experience / reference to be able to >put product names to these capabilities. Would you "name names" please? I'll >create a diversion to take all the flames while you do that... (c: 68000 series has pretty symmetric instruction set (orthoganol). ie Moving from register to memory and vice versa is symmetric there are minimal exceptions. There are microntroller variants of processors that use 68000 instruction set. Having a lot of registers is a bonus, 16 to 32 is ideal for the vast bulk on microcontroller apps, can get away with 4 or even 2 if you are keen. Basically, for a beginner, you'd want an instruction set that works 'both ways' with registers, memory and IO ports, you dont want one with lots of lumpy exceptions or stack size restrictions or memory address or io restrictions - because if you are doing assembler you dont want to worry about that many until you are proficient, which usually happens fairly soon once you get stuck into it... -- Regards Mike * VK/VL Commodore FuseRails that wont warp or melt with fuse failure indication and now with auto 10-15 min timer for engine illumination option. * VN, VP, VR Models with relay holder in progress. * Twin Tyres to suit most sedans, trikes and motorcycle sidecars http://niche.iinet.net.au
From: John Barrett on 18 Mar 2007 02:04 "Mike" <erazmus(a)iinet.net.au> wrote in message news:45fcb473$0$17581$5a62ac22(a)per-qv1-newsreader-01.iinet.net.au... > In article <0001HW.C220350A0041BFCBF01826C8(a)news.sf.sbcglobal.net>, > incognito(a)yahoo.com says... >> >>> Actually, just about anything that has a stack-oriented architecture, or >>> a register-oriented architecture with an orthogonal instruction set and >>> decent indexing. >> >>Being a beginner in all this, I have no experience / reference to be able >>to >>put product names to these capabilities. Would you "name names" please? >>I'll >>create a diversion to take all the flames while you do that... (c: > > 68000 series has pretty symmetric instruction set (orthoganol). > > ie Moving from register to memory and vice versa is symmetric there are > minimal exceptions. There are microntroller variants of processors that > use 68000 instruction set. > > Having a lot of registers is a bonus, 16 to 32 is ideal for the vast bulk > on microcontroller apps, can get away with 4 or even 2 if you are keen. > > Basically, for a beginner, you'd want an instruction set that works 'both > ways' with registers, memory and IO ports, you dont want one with lots of > lumpy exceptions or stack size restrictions or memory address or io > restrictions - because if you are doing assembler you dont want to worry > about that many until you are proficient, which usually happens fairly > soon > once you get stuck into it... > > GEEEZ -- I gave up writing ASM for the 1st cut about 20 years ago -- the compilers available even then were efficient enough that you only needed to get down and dirty for the most critical timing dependent code.. there just isnt a point in starting off with ASM considering that C maps almost 1-to-1 to most assembly languages for most of its internal features. And the WinAVR C compiler makes it real easy to embed ASM right in the C code so I can do it in C first, then convert just the parts that need it in place with a perfectly working and tested "flow chart" right in front of me. In addition.. for 99% of apps, you'll never bother with ASM because the compiled code will work right off and nothing will need to be hand optimized... you've gotta be right on the ragged edge of what the chip is capable of before ASM is going to help you, and 99% of apps wont even come close to that limit.
From: John E. on 18 Mar 2007 03:03
> ie Moving from register to memory and vice versa is symmetric there are > minimal exceptions. There are microntroller variants of processors that > use 68000 instruction set. > > Having a lot of registers is a bonus, 16 to 32 is ideal for the vast bulk > on microcontroller apps, can get away with 4 or even 2 if you are keen. > > Basically, for a beginner, you'd want an instruction set that works 'both > ways' with registers, memory and IO ports, you dont want one with lots of > lumpy exceptions or stack size restrictions or memory address or io > restrictions - because if you are doing assembler you dont want to worry > about that many until you are proficient, which usually happens fairly soon > once you get stuck into it... Names! Names! Names! (please). I agree with what you say, but I need the benefit of y'all's experience. Which controller "variants of processors that use 68000 instruction set" and which don't do "lumpy exceptions or stack size restrictions..." etc. Just need to know what name to call these lovelies by. -- John English |