Which uController to learn?
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From: John Barrett on 23 Mar 2007 12:57 "krw" <krw(a)att.bizzzz> wrote in message news:MPG.206da510f80eb5e298a216(a)news.individual.net... > In article <1307g1itfi6is9d(a)news.supernews.com>, spam-not(a)nowhere.com > says... >> jasen wrote: >> > On 2007-03-16, Anthony Fremont <spam-not(a)nowhere.com> wrote: >> >> TT_Man wrote: >> >>>> As you said, PIC is king and it is for a reason, they work. >> >>>> >> >>> Only if you can get to grips with the appalling op code set..... OK >> >>> if you can program in C , I suppose.I can't/won't >> >> >> >> I only do assembler on the PIC too. What's wrong with the op-code >> >> set? It's RISC, >> > >> > no it's not, it has too few registers to qualify. >> >> By whose definition? It stands for Reduced Instruction Set. 35 >> instructions is pretty reduced IMO. > > Actually, it stands for "Reduced Instruction Set Complexity". It has > nothing to do with the number of instructions (PowerPC is certainly > RISC, yet has hundreds of instructions in even more varieties), > rather the complexity of the instructions. For example, no > arithmetic operations on memory are allowed, only load/stores. > >> >> it has 35 instructions, it's not supposed to be luxurious. It's >> >> supposed to be functional and fast....it succeeds. >> > >> > It always seemed kind of awkward and slow slow to me. >> >> Compared to what? 10MIPs on a few mA is pretty good in my book. >> > -- > Keith RISC essentially means that EVERY instruction takes ONE clock cycle, so your clock speed is your IPS -- CISC chips like the 80x86 take anywhere from 4-??? instructions per clock, they internally decode instructions through a micro-code rom in the CPU that sequences the internal processing elements of the chip through the steps neccessary to perform the instruction -- for instance -- a single instruction may read memory, add it to a register, and write the result back to memory -- all in one instruction, but across multiple clock cycles. Therefore there are things a CISC chip can do in one ASM instruction that a RISC chip cannot do, simply because there is no way to perform the operation in a single clock cycle... for instance -- the 80x86 has a single instruction memory copy capability for moving data around -- makes things a little easier on the compiler developers.
From: John Barrett on 23 Mar 2007 13:03 "Anthony Fremont" <spam-not(a)nowhere.com> wrote in message news:1307jeqbvqfpv61(a)news.supernews.com... > jasen wrote: >> On 2007-03-17, bungalow_steve(a)yahoo.com <bungalow_steve(a)yahoo.com> >> wrote: >> >>> the AVR series hasen't increased in performance in years (speed, a/d >>> resolution, DMA, fifo buffers, divide instructions etc). >> >> Many of them are doing 20 MIPS now, that wasn't available two years >> ago, built-in full speed USB is new too, > > 20 MIPS, on a MEGA. Those aren't backwards compatible with the tradition > AVRs are they? > >> It's an 8-bit microcontroller it doesn't need that extra stuff ... > > Speak for yourself. Since when is A/D resolution not important for an 8 > bitter? > AVR32 based 32-bit MCU/DSP Vectored multiplier co-processor, 32 KB on-chip SRAM, 16 KB instruction and 16 KB data caches, MMU, DMA controller. Peripherals include a 16-bit stereo audio DAC, 2048x2048 pixel TFT/STN LCD controllers, 480 Mbps USB 2.0 with on chip transceivers (PHY) and, two 10/100 Ethernet MACs. Serial interfaces include RS232, USART, I2S, AC97, TWI/I2C, SPI, PS/2 and several synchronous serial modules (SSC) supporting most serial communication protocols. sounds like a bit more than an 8-bitter to me !!
From: krw on 23 Mar 2007 13:09 In article <BFTMh.81$un.9(a)trnddc03>, ke5crp1(a)verizon.net says... > > "krw" <krw(a)att.bizzzz> wrote in message > news:MPG.206da510f80eb5e298a216(a)news.individual.net... > > In article <1307g1itfi6is9d(a)news.supernews.com>, spam-not(a)nowhere.com > > says... > >> jasen wrote: > >> > On 2007-03-16, Anthony Fremont <spam-not(a)nowhere.com> wrote: > >> >> TT_Man wrote: > >> >>>> As you said, PIC is king and it is for a reason, they work. > >> >>>> > >> >>> Only if you can get to grips with the appalling op code set..... OK > >> >>> if you can program in C , I suppose.I can't/won't > >> >> > >> >> I only do assembler on the PIC too. What's wrong with the op-code > >> >> set? It's RISC, > >> > > >> > no it's not, it has too few registers to qualify. > >> > >> By whose definition? It stands for Reduced Instruction Set. 35 > >> instructions is pretty reduced IMO. > > > > Actually, it stands for "Reduced Instruction Set Complexity". It has > > nothing to do with the number of instructions (PowerPC is certainly > > RISC, yet has hundreds of instructions in even more varieties), > > rather the complexity of the instructions. For example, no > > arithmetic operations on memory are allowed, only load/stores. > > > >> >> it has 35 instructions, it's not supposed to be luxurious. It's > >> >> supposed to be functional and fast....it succeeds. > >> > > >> > It always seemed kind of awkward and slow slow to me. > >> > >> Compared to what? 10MIPs on a few mA is pretty good in my book. > >> > > -- > > Keith > > RISC essentially means that EVERY instruction takes ONE clock cycle, so your > clock speed is your IPS -- CISC chips like the 80x86 take anywhere from > 4-??? instructions per clock, they internally decode instructions through a > micro-code rom in the CPU that sequences the internal processing elements of > the chip through the steps neccessary to perform the instruction -- for > instance -- a single instruction may read memory, add it to a register, and > write the result back to memory -- all in one instruction, but across > multiple clock cycles. Nope. RISC == "Reduced Instruction Set Complexity". It has nothing to do with IPS. RISC is a philosophy. IPS is a design trade-off. The PowerPC *is* a RISC architecture. Some PowerPC implementations (e.g.. PPC750) tend to be one-cycle through the execution unit (plus decode, etc) where the Power5 is the same architecture and may be 5 to 15 cycles through the execution unit. The x86 processors have memory reference arithmetec instructions (e.g.. ADD R,<memory>, thus CISC (the opposite of RISC). PowerPC has no like instruction. > Therefore there are things a CISC chip can do in one ASM instruction that a > RISC chip cannot do, simply because there is no way to perform the operation > in a single clock cycle... for instance -- the 80x86 has a single > instruction memory copy capability for moving data around -- makes things a > little easier on the compiler developers. > It's RISC, not because it can do more than one thing per instruction, but because it can operate on memory with one instruction. BTW, RISC compilers are *far* easier to write; one of the reasons RISC was invented. RISC processors tend to be register rich, since they cannot operate on memory. -- Keith
From: DJ Delorie on 23 Mar 2007 13:34 krw <krw(a)att.bizzzz> writes: > BTW, RISC compilers are *far* easier to write; This is an invalid generalization. Compiler complexity depends on many factors, and the raw size of the instruction set isn't even near the top of the list. Specialization is a more key factor, and RISC chips tend to have more specialized instructions. A CISC chip, for example, can usually add anything to anything, whereas RISC chips can only add registers, and sometimes add constants to a register. The top of the list is usually "customer's requests for unique functionality".
From: krw on 23 Mar 2007 14:13
In article <xn4pob3lui.fsf(a)delorie.com>, dj(a)delorie.com says... > > krw <krw(a)att.bizzzz> writes: > > BTW, RISC compilers are *far* easier to write; > > This is an invalid generalization. Compiler complexity depends on > many factors, and the raw size of the instruction set isn't even near > the top of the list. I never said it was! Perhaps you'd like to read what I wrote. RISC <> small_instruction_set was one of my main points. > Specialization is a more key factor, and RISC > chips tend to have more specialized instructions. Nonsense. If anything RISC's instructions are less specialized. There aren't any string moves to memory, for instance. > A CISC chip, for > example, can usually add anything to anything, whereas RISC chips can > only add registers, and sometimes add constants to a register. That is pretty much the definition of RISC, so yes... They generally have LOTSA register though. It's easier scheduling data when you have lots of places to put it. Register management is more complex with CISC processors. > The top of the list is usually "customer's requests for unique > functionality". Huh? When does a customer request functionality from a compiler? -- Keith |