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From: Griffin on 5 Jan 2010 16:36
I'm working on a ML402 (Virtex-4) EDK project which has one custom IP
("event_getter") that was created using the EDK Create Peripheral
Wizard and then I added my code (included below) to the generated
user_logic.vhdl file. I am able to generate a netlist without issue,
but when I compile the bitstream, I get the following warnings:

WARNING:LIT:243 - Logical network my_peripheral_pin_0_IBUF has no
load.

and

WARNING:MapLib:701 - Signal my_peripheral_pin<0> connected to top
level port my_peripheral_pin<0> has been removed.

and it is repeated for pins my_peripheral_pin<1 - 6> (ie, all my
external pins). Synthesis continues, however, and a bitstream is
generated.

My peripheral code is:

pin_in: std_logic_vector(0 to 6);

[...]

signal pixel_0 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_1 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_2 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_3 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_4 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_5 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_6 : std_logic_vector(0 to 15):= (others => '0');

signal s0: std_logic_vector(0 to C_SLV_DWIDTH-1):= (others => '0');
signal s1: std_logic_vector(0 to C_SLV_DWIDTH-1):= (others => '0');
signal s2: std_logic_vector(0 to C_SLV_DWIDTH-1):= (others => '0');
signal s3: std_logic_vector(0 to C_SLV_DWIDTH-1):= (others => '0');

[...]

-- purpose: peek at pixels and increment corresponding counters
-- type : combinational
-- inputs : pin_in(i)
-- outputs: pixel_(i)

check0: process (pin_in(0)) is
begin
if rising_edge(pin_in(0)) then
pixel_0 <= pixel_0 + '1';
s0(0 to 15) <= pixel_0;
end if;
end process;

check1: process (pin_in(1)) is
begin
if rising_edge(pin_in(1)) then
pixel_1 <= pixel_1 + '1';
s0(16 to 31) <= pixel_1;
end if;
end process;

(the above two blocks are repeated for pixels 2-6)

-- purpose: update registers to pixel count values
-- inputs : Bus2IP_Clk
-- outputs: slv_reg(i)
UPDATE_REGISTERS : process (Bus2IP_Clk) is
begin -- process
slv_reg0 <= s0;
slv_reg1 <= s1;
slv_reg2 <= s2;
slv_reg3 <= s3;
end process;



slv_reg0..3 are read out by EDK's automatically generated ReadReg
functions so I can access them from the C-level part of my project.


Firstly, I'm not sure what the first message means, no where in the
code I wrote have I defined anything including '_IBUF' (albeit I
suspect it to be something EDK generates automatically, in such a
case, can someone tell me what it is?

Secondly, if I understand correctly, the pins of my custom peripheral
are being removed from the project. I've looked around the internet a
bit and suspect this might be done due to auto-optimization, but
considering that these pins are, indeed, being used in the user_logic
file, and the registers that they store their values in are being read
out by my applicateion C code, I'm not sure why this would happen.
Does anyone have an idea why EDK could be removing my pins?

I assigned them to be external ports in EDK via System Assembly View -
> Ports -> My_peripheral -> (net column menu) Make External.

Thanks in advance,

Sean.

From: Mike Treseler on 7 Jan 2010 18:19
Griffin wrote:

> Secondly, if I understand correctly, the pins of my custom peripheral
> are being removed from the project. I've looked around the internet a
> bit and suspect this might be done due to auto-optimization, but
> considering that these pins are, indeed, being used in the user_logic

It's not enough for a signal to be used by a process.
If a top level output port is not driven by a process -- no output pin.
If a top input input port is not read by a process -- no input pin.


> file, and the registers that they store their values in are being read
> out by my application C code,

correctly or all zeros?

-- Mike Treseler
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