Why does Intel favor thin rectangular CPUs?
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From: MitchAlsup on 10 Mar 2010 12:33 On Mar 10, 1:00 am, "Andy \"Krazy\" Glew" <ag-n...(a)patten-glew.net> wrote: > I think that no longer having the prospect of visiting Haifa is the only thing I really miss about Intel. A very beautiful place to live and work, both the city and the country in general. Mitch
From: Tim McCaffrey on 10 Mar 2010 14:03 In article <4B974355.1010107(a)patten-glew.net>, ag-news(a)patten-glew.net says... > >Robert Myers wrote: > >> A machine that achieves 5% efficiency doing a bog-standard problem has >> little right to claim to be super in any respect. That's my mantra. > >I've been lurking and listening and learning, but, hold on: this is silly. > >Utilization has nothing to do with "super-ness". Cost effectiveness is what matters. > >When you say 5% efficient, I assume that you are talking about as a fraction of peak flops >. > >But if the flops are cheap compared to the bandwidth, then it may very well make sense to >add lots of flops. You might >want to add more bandwidth, but if you can add a 1% utilized flop and eke a little bit mor >e out of the expensive >interconnect... > >What you really need to do is show that there are better architectures, that deliver the b >andwidth you want, as well as >getting better utilization. > >OK, now I'll step back and listen some more. So, MoSys just announced the Bandwidth Engine: 15 ns access, 16 GB/s, 64 MBytes Designed for network routers/switches. Watch the webcast on www.mosys.com (you can skip to the BE presentation). - Tim
From: Del Cecchi on 10 Mar 2010 21:33 "Tim McCaffrey" <timcaffrey(a)aol.com> wrote in message news:hn8qei$v8b$1(a)USTR-NEWS.TR.UNISYS.COM... > In article <4B974355.1010107(a)patten-glew.net>, > ag-news(a)patten-glew.net says... >> >>Robert Myers wrote: >> >>> A machine that achieves 5% efficiency doing a bog-standard problem >>> has >>> little right to claim to be super in any respect. That's my >>> mantra. >> >>I've been lurking and listening and learning, but, hold on: this is >>silly. >> >>Utilization has nothing to do with "super-ness". Cost effectiveness >>is what > matters. >> >>When you say 5% efficient, I assume that you are talking about as a >>fraction > of peak flops >>. >> >>But if the flops are cheap compared to the bandwidth, then it may >>very well > make sense to >>add lots of flops. You might >>want to add more bandwidth, but if you can add a 1% utilized flop >>and eke a > little bit mor >>e out of the expensive >>interconnect... >> Interesting part. As I said a few days ago, bandwidth costs money. Latency is with us always. Is each chip 16 bits wide, time 10G/sec? The pictures were a little confusing, as to whether the thing with all of the 32k*72 bit arrays and the 16 bits in and out was a chip or a subsystem. Chip is most likely, but just checking. del >>What you really need to do is show that there are better >>architectures, that > deliver the b >>andwidth you want, as well as >>getting better utilization. >> >>OK, now I'll step back and listen some more. > > > So, MoSys just announced the Bandwidth Engine: > 15 ns access, 16 GB/s, 64 MBytes > Designed for network routers/switches. > > Watch the webcast on www.mosys.com (you can skip to the BE > presentation). > > - Tim >
From: Andrew Reilly on 11 Mar 2010 06:03 On Wed, 10 Mar 2010 21:49:26 -0800, Robert Myers wrote: > The linpack benchmark shows NOTHING, except that the processors are in > the same room and connected. Why did you bring it up, then? It *is* a fairly close approximation to the "guaranteed not to be exceeded" peak flops, which is interesting to know for some sorts of code. Cheers, -- Andrew
From: Tim McCaffrey on 11 Mar 2010 09:26
In article <7vr2unF9psU1(a)mid.individual.net>, delcecchi(a)gmail.com says... > > >"Tim McCaffrey" <timcaffrey(a)aol.com> wrote in message >news:hn8qei$v8b$1(a)USTR-NEWS.TR.UNISYS.COM... >> >> So, MoSys just announced the Bandwidth Engine: >> 15 ns access, 16 GB/s, 64 MBytes >> Designed for network routers/switches. >> >> Watch the webcast on www.mosys.com (you can skip to the BE >> presentation). >> >> > >Interesting part. As I said a few days ago, bandwidth costs money. >Latency is with us always. > >Is each chip 16 bits wide, time 10G/sec? The pictures were a little >confusing, as to whether the thing with all of the 32k*72 bit arrays >and the 16 bits in and out was a chip or a subsystem. > >Chip is most likely, but just checking. > Chip. They claim 2 billion access/second for 72 bit words across 16 10G links. -Tim |