Prev: Daubechies-4 wavelet transform in MATLAB
Next: Download & Read your favorite ebooks with eReader JE200
From: glen herrmannsfeldt on 14 Apr 2010 19:38
GreenXenon <glucegen1x(a)gmail.com> wrote:
(snip)

> Twin-Transistor RAM is a new technology.

> http://en.wikipedia.org/wiki/Twin_Transistor_RAM

> It has the least duration of data remanence when the power is offed.
> That's why I want it.

There have been discussions about possible data retention in
both SRAM and DRAM, if you keep constant data for a long time.

-- glen
From: Steve Pope on 14 Apr 2010 19:49
glen herrmannsfeldt <gah(a)ugcs.caltech.edu> wrote:

>There have been discussions about possible data retention in
>both SRAM and DRAM, if you keep constant data for a long time.

Good point -- you might see some carrier trapping in a capacitor that
has been always charged, relative one that has not. But you
won't see a voltage signal -- an actual charge -- after a period of
usually seconds or minutes.

The first problem, trapping of carriers or migration of atoms
of some sort, is going to impact twin-transistor RAMs also.

Steve
From: glen herrmannsfeldt on 14 Apr 2010 22:17
Steve Pope <spope33(a)speedymail.org> wrote:
> glen herrmannsfeldt <gah(a)ugcs.caltech.edu> wrote:

>>There have been discussions about possible data retention in
>>both SRAM and DRAM, if you keep constant data for a long time.

> Good point -- you might see some carrier trapping in a capacitor that
> has been always charged, relative one that has not. But you
> won't see a voltage signal -- an actual charge -- after a period of
> usually seconds or minutes.

I remember in 1976 working with an S100 based system with a
VDM1 display board. As it powers on, the display logic is
active before the display memory is cleared. (It seems like
systems today don't do that.) I had wondered if the power up
value was always (mostly) the same. For SRAM, it would seem that
any slight difference between the transistors in the sell would
bias the startup such that it would tend to power up the same way.

The idea, then, came for having an initialized RAM, somewhat like
what we now have in the FPGA.

It is a little less obvious for DRAM, but it might be that, as you
say, trapped charge might effect the initial value enough that it
would power on differently. If not, you can take the chip out
and measure trapped charge with various kinds of probes.

> The first problem, trapping of carriers or migration of atoms
> of some sort, is going to impact twin-transistor RAMs also.

You have to be sure that the same data doesn't stay in place
for a long time.

> Steve
From: Michael Plante on 15 Apr 2010 14:56
glen herrmannsfeldt wrote:
>Steve Pope <spope33(a)speedymail.org> wrote:
>> glen herrmannsfeldt <gah(a)ugcs.caltech.edu> wrote:
>
>>>There have been discussions about possible data retention in
>>>both SRAM and DRAM, if you keep constant data for a long time.
>
>[...]
>
>> The first problem, trapping of carriers or migration of atoms
>> of some sort, is going to impact twin-transistor RAMs also.
>
>You have to be sure that the same data doesn't stay in place
>for a long time.


If this is the primary concern, and as long as people are fantasizing about
future technologies, would it be possible to have a refresh controller that
flips all bits on refresh, remembering which regions have been refreshed an
odd number of times, and selectively inverts them on read-out? I only know
a little about DRAM, so I could be way off...

Michael


From: Steve Pope on 15 Apr 2010 14:59
Michael Plante <michael.plante(a)n_o_s_p_a_m.gmail.com> wrote:

>glen herrmannsfeldt wrote:

>>Steve Pope <spope33(a)speedymail.org> wrote:

>>> The first problem, trapping of carriers or migration of atoms
>>> of some sort, is going to impact twin-transistor RAMs also.

>>You have to be sure that the same data doesn't stay in place
>>for a long time.

>If this is the primary concern, and as long as people are fantasizing about
>future technologies, would it be possible to have a refresh controller that
>flips all bits on refresh, remembering which regions have been refreshed an
>odd number of times, and selectively inverts them on read-out? I only know
>a little about DRAM, so I could be way off...

You could do this; you could also re-write entire blocks of memory
with a different scrambling pattern XOR's in each time.

But such refresh controllers would be an excellent target for
exfiltration techniques. :-)


Steve
 |  Next  |  Last
Pages: 1 2 3 4
Prev: Daubechies-4 wavelet transform in MATLAB
Next: Download & Read your favorite ebooks with eReader JE200