Wrong DDR communication
in [FPGA]
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From: Pierpaolo on 26 Mar 2010 07:43 Hi everyone, I'm implenting a design on a Virtex4 that has to follow the communication of a processor with the ddr memory that is on the board. The board that I'm using is an Avnet ADS-XLX-V4LX-DEV160. The bridge that link the processor with the memory at the end has a Xilinx component IOBUF to transmit and receive data and strobe (bidirectional). It looks that all the signal sent to the memory are right, but the problem is that the data signals received from the memory are always to 1 like if the memory is turned off. I checked the file .ucf for the connection and it looks right. Does someone know what could be the problem? Thanks Pierpaolo --------------------------------------- Posted through http://www.FPGARelated.com
From: George on 29 Mar 2010 07:43 What version of ISE/EDK are you using? Are you using a core or did you write your own interface to the DDR?
From: Pierpaolo on 31 Mar 2010 11:06 >What version of ISE/EDK are you using? Are you using a core or did >you write your own interface to the DDR? > Hi! The version of ISE that I'm using is 9.2. I'm using a DDR controller found on www.opencores.org for communication with a memory that is on board with a Virtex2 then modified for my board with a Virtex4. --------------------------------------- Posted through http://www.FPGARelated.com
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