XUPV5-LX110T, DDR2, and EDK (10.1 to be precise)
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From: mmcshmi11 on 14 Dec 2009 03:54 Hi everyone, there has been a lot of talk about this same question I'm about to ask, but it is spread out over many different locations on the internet and I can't find a real answer... I am trying to interface the supplied 256MB DDR2 module (MT4HTF3264H-53E) with the XUPV5-LX110T board. I'm using EDK 10.1 and I can add an MPMC core, but the BSB only has the LX50T device listed, so when it runs MIG it creates a UCF file that gives the following error when compiled: ------------------------------------------------------------------------------ ERROR:Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ<13>" and IODELAY component "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into the same I/O tile in order to route net "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g en_dq[13].u_iob_dq/dq_in". The following issue has been detected: Some of the logic associated with this structure is locked. This should cause the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56 where we must place IODELAY DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement requirements of this logic. IODELAY DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which makes this design unplaceable. ------------------------------------------------------------------------------ There has been the suggestion that opening CORE generator and creating a new MIG project (MIG v2.3 in my case) may work because it does contain the LX110T device. However, this new file needs to have its LOC constraints changed as well to specifically fit the XUPV5-LX110T board. Can somebody point me in the right direction for fixing this, maybe I just need to learn more about I/O tiles, banks, and what it means to have "Some of the logic associated with this structure locked". ANY help would be greatly appreciated, Thanks --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com |