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From: moogyd on 19 Jan 2010 13:14
Hello,

I am seeing a problem using ISE. I have a verilog top level with pins
including N0, N1, N2, N3, N4 (similar for PX, SX and MX)

I add a LOC constraint in the UCF file for all pins. For some reason,
the tool seems to be confused by N1, N2, N3 and N4 (but not N0, or any
of PX, SX, MX)

WARNING:NgdBuild:483 - Attribute "LOC" on "N1" is on the wrong type of
object.
Please see the Constraints Guide for more information on this
attribute.

When I report the pinout at the end of the P&R, pins N1..N4 have
disappeared, and I have some new pins (N31, N18, N21, N18)

My *guess* is that Xilinx uses Nx (x>0) for internal netnames, and it
is getting confused.

Can anyone confirm and suggest a workaround? (I don't want to change
the pin names)

Thanks,

Steven



From: Gabor on 20 Jan 2010 11:06
On Jan 19, 1:14 pm, moogyd <moo...(a)yahoo.co.uk> wrote:
> Hello,
>
> I am seeing a problem using ISE. I have a verilog top level with pins
> including N0, N1, N2, N3, N4 (similar for PX, SX and MX)
>
> I add a LOC constraint in the UCF file for all pins. For some reason,
> the tool seems to be confused by N1, N2, N3 and N4 (but not N0, or any
> of PX, SX, MX)
>
> WARNING:NgdBuild:483 - Attribute "LOC" on "N1" is on the wrong type of
> object.
>    Please see the Constraints Guide for more information on this
> attribute.
>
> When I report the pinout at the end of the P&R, pins N1..N4 have
> disappeared, and I have some new pins (N31, N18, N21, N18)
>
> My *guess* is that Xilinx uses Nx (x>0) for internal netnames, and it
> is getting confused.
>
> Can anyone confirm and suggest a workaround? (I don't want to change
> the pin names)
>
> Thanks,
>
> Steven

The obvious workaround is to change your pin names...
I'm pretty sure you don't need to change them much.
Something like N_1, N_2. . .
or you could turn them into a bus
inout [4:0] N,
.. . .
Then in the .ucf you'd have N<0>, N<1>, etc.
Or you can try ISE 10.1 and see if the "problem" has been "fixed."

Regards,
Gabor
From: moogyd on 4 Feb 2010 09:18
On 19 Jan, 19:14, moogyd <moo...(a)yahoo.co.uk> wrote:
> Hello,
>
> I am seeing a problem using ISE. I have a verilog top level with pins
> including N0, N1, N2, N3, N4 (similar for PX, SX and MX)
>
> I add a LOC constraint in the UCF file for all pins. For some reason,
> the tool seems to be confused by N1, N2, N3 and N4 (but not N0, or any
> of PX, SX, MX)
>
> WARNING:NgdBuild:483 - Attribute "LOC" on "N1" is on the wrong type of
> object.
>    Please see the Constraints Guide for more information on this
> attribute.
>
> When I report the pinout at the end of the P&R, pins N1..N4 have
> disappeared, and I have some new pins (N31, N18, N21, N18)
>
> My *guess* is that Xilinx uses Nx (x>0) for internal netnames, and it
> is getting confused.
>
> Can anyone confirm and suggest a workaround? (I don't want to change
> the pin names)
>
> Thanks,
>
> Steven

Hi,

FYI, this problem seems to be fixed with ISE 11.1

Steven
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