Xilinx ISE Webpack and Pipeline Optimization
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From: Tim Wescott on 3 Aug 2010 13:25 Here's a naive question, from a sometime FPGA user: A long time ago, a friend of mine who does _real_ digital design work was telling me how cool the (then new) Mentor tools were, because you could do a whole bunch of natural-looking combinational Verilog code in a module, then at the very end you could put in a bunch of register delays, and the tools would figure out how to distribute the delays in your combinational code to get a nicely pipelined bit of logic. Has this nifty technology migrated into Xilinx tools? Or if I need pipelining, do I need to figure it out myself? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
From: Rob Gaddi on 3 Aug 2010 13:32 On 8/3/2010 10:25 AM, Tim Wescott wrote: > Here's a naive question, from a sometime FPGA user: > > A long time ago, a friend of mine who does _real_ digital design work > was telling me how cool the (then new) Mentor tools were, because you > could do a whole bunch of natural-looking combinational Verilog code in > a module, then at the very end you could put in a bunch of register > delays, and the tools would figure out how to distribute the delays in > your combinational code to get a nicely pipelined bit of logic. > > Has this nifty technology migrated into Xilinx tools? Or if I need > pipelining, do I need to figure it out myself? > Theoretically yes, practically I've had great difficulty getting the tools to distribute any more than one level of pipeline delay. -- Rob Gaddi, Highland Technology Email address is currently out of order
From: Manny on 3 Aug 2010 16:15 On Aug 3, 6:25 pm, Tim Wescott <t...(a)seemywebsite.com> wrote: > Here's a naive question, from a sometime FPGA user: > > A long time ago, a friend of mine who does _real_ digital design work > was telling me how cool the (then new) Mentor tools were, because you > could do a whole bunch of natural-looking combinational Verilog code in > a module, then at the very end you could put in a bunch of register > delays, and the tools would figure out how to distribute the delays in > your combinational code to get a nicely pipelined bit of logic. > > Has this nifty technology migrated into Xilinx tools? Or if I need > pipelining, do I need to figure it out myself? You have to always be cautious of what the tools can or can not do for you. My experience tells me that cheap tools are better off fed the design with a spoon. Then comes a host of other problems to do with bugs everywhere, e.g. a design with a MACC has to be broken into separate multiply and accumulate blocks and then retimed. Pure joy! -Momo
From: Steve Pope on 3 Aug 2010 16:40 On Aug 3, 6:25�pm, Tim Wescott <t...(a)seemywebsite.com> wrote: > Here's a naive question, from a sometime FPGA user: > > A long time ago, a friend of mine who does _real_ digital design work > was telling me how cool the (then new) Mentor tools were, because you > could do a whole bunch of natural-looking combinational Verilog code in > a module, then at the very end you could put in a bunch of register > delays, and the tools would figure out how to distribute the delays in > your combinational code to get a nicely pipelined bit of logic. > > Has this nifty technology migrated into Xilinx tools? �Or if I need > pipelining, do I need to figure it out myself? Register retiming. All the synthesizers do this. Steve
From: Andy on 3 Aug 2010 18:09
But how many re-time over more than one clock cycle? Many can only move logic +/- 1 clock cycle, and some don't do it unless the original design won't meet timing. Andy |