Xilinx PCI-Express Endpoint Block IP
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From: water9580 on 4 Nov 2007 09:03 There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx PCI-Express Endpoint Block IP. it means that it needs 250MHz clk.In general,it is impossible to achieve 250Mhz clk with large design.So,we need 16bit interface wrapper so that the clk can be reduced 125Mhz. it is very easy to implement.is there avaliable 16bit wrapper?
From: sovan on 4 Nov 2007 15:45
I think it should be possible to design a 16-bit interface wrapper around the GTP. Buf if you are using the PCIE_EP hard block then the Transceiver interface is 8-bit PIPE interface. So we don't gain much by having a 16-bit interface wrapper for GTP. In my design I have registers in all the connections between PCIE_EP and GTP. It works fine for x1 and x4. There wasn't any timing issue. My core_clock is 250 MHz and user_clock is 125 MHz. -Sovan. |