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From: Karel Deprez on 15 Sep 2009 12:10
Hello,

I have been trying to fit a deserializer into a Spartan 6 but I am
running into some problems:
- I am able to fit my design if the deserializer is on a top or a
bottom bank. I can't get it fit when the deserializer is on the left
or the right bank. There seems to be a problem with the BUFIO2.

This is the error:
ERROR:Place - SIO has over-constrained componet
g_LTC2173Decoder[0].i_LTC2173Decoder/i_LVDSClockBuffer/i_BUFIO2 to
have to
placeable sites. Constraints come from driver constraints AND load
IO
constraints

This error message doesn't really help me...

In FPGA editor I find the BUFIO2's on all sides (top, bottom, left and
right) but it looks as if these on the left and right side are a
little different (they have no negative input).


- The report
From: Karel Deprez on 17 Sep 2009 07:01
Does anybody know if this is a known issue, I couldn't find
information in the manuals...
From: Uwe Bonnes on 17 Sep 2009 07:30
Karel Deprez <karel.deprez(a)skynet.be> wrote:
> Does anybody know if this is a known issue, I couldn't find
> information in the manuals...

Did you try 11.3? It just cam out, you have to download a 2+ GB
files. Perhaps is addresses the issue.
--
Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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