Xilinx project failed timing constraints
in [FPGA]
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From: Sharmila on 5 May 2010 18:47 I am working on bit of a complex DSP design and generating .vhdl files based on the MATLAB/Simulink design. These vhdl files are then imported into a Xilinx project file and mapped, placed, routed, testing for timing to eventually generate a bit file for a Virtex SX95T. When I get a failed timing constraint, I manually place slices or add latency to meet timing. I succeed in fixing this failed timing constraint but get a new one in a unrelated block. My question is if this new timing constraint is a side effect of my change or if Xilinx does sequential failed timing error reporting ? I'm running Xilinx ISE 10.1.03 Foundation and the appropriate sysgen. Regards, Sharmila
From: Patrick Maupin on 5 May 2010 23:23 On May 5, 5:47 pm, Sharmila <sharmi...(a)gmail.com> wrote: > I am working on bit of a complex DSP design and generating .vhdl files > based on the MATLAB/Simulink design. These vhdl files are then > imported into a Xilinx project file and mapped, placed, routed, > testing for timing to eventually generate a bit file for a Virtex > SX95T. When I get a failed timing constraint, I manually place slices > or add latency to meet timing. > I succeed in fixing this failed timing constraint but get a new one in > a unrelated block. My question is if this new timing constraint is a > side effect of my change or if Xilinx does sequential failed timing > error reporting ? > I'm running Xilinx ISE 10.1.03 Foundation and the appropriate sysgen. > Regards, > Sharmila Under the properties tab for the post-PAR timing analysis, you can tell it how many paths per clock you want to see. I think the default is only 3. You can also ask it to perform "advanced analysis" and tell it you want a "verbose report" and get information on paths that pass, but are marginal. But the whole thing is kind of like a balloon animal -- press over here, and it will pop out over there. That certainly could be happening to you. Regards, Pat
From: Fredxx on 6 May 2010 05:18 Patrick Maupin wrote: > On May 5, 5:47 pm, Sharmila <sharmi...(a)gmail.com> wrote: >> I am working on bit of a complex DSP design and generating .vhdl >> files based on the MATLAB/Simulink design. These vhdl files are then >> imported into a Xilinx project file and mapped, placed, routed, >> testing for timing to eventually generate a bit file for a Virtex >> SX95T. When I get a failed timing constraint, I manually place slices >> or add latency to meet timing. >> I succeed in fixing this failed timing constraint but get a new one >> in a unrelated block. My question is if this new timing constraint >> is a side effect of my change or if Xilinx does sequential failed >> timing error reporting ? >> I'm running Xilinx ISE 10.1.03 Foundation and the appropriate sysgen. >> Regards, >> Sharmila > > Under the properties tab for the post-PAR timing analysis, you can > tell it how many paths per clock you want to see. I think the default > is only 3. You can also ask it to perform "advanced analysis" and > tell it you want a "verbose report" and get information on paths that > pass, but are marginal. > > But the whole thing is kind of like a balloon animal -- press over > here, and it will pop out over there. That certainly could be > happening to you. > Good advice and also my experience. To speed up synthesis time and fitting, I often compile the modules seapartely with a tight timing constraint in a corresponding UCF file. If timing is critical, the iteration design change - fit cycle time is greatly shortened, and critical areas can be identified with a tighter than design required timing constraint. Policies of multiple cycle constraints can also be made. It's all a bit late when it takes 1/2 hour to find out your design doesn't meet a timing constraint!
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