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From: firefox3107 on 1 Jul 2010 00:15
Hey,

I found an amazing async fifo concept on the xilinx homepage.
It looks that the latency to share data between clock domains is
reduced to one cycle.
But I'm asking if the setup + hold times are always met. I admit that
setting the empty flag is correct but what about releasing, which is
caused by write clock, thus asynchrous?
From: firefox3107 on 1 Jul 2010 00:47
Sorry, I have forgotten to add the link:
http://www.xilinx.com/support/documentation/application_notes/xapp175.pdf
From: glen herrmannsfeldt on 1 Jul 2010 01:10
firefox3107 <firefox3107(a)gmail.com> wrote:

> I found an amazing async fifo concept on the xilinx homepage.
> It looks that the latency to share data between clock domains is
> reduced to one cycle.
> But I'm asking if the setup + hold times are always met. I admit that
> setting the empty flag is correct but what about releasing, which is
> caused by write clock, thus asynchrous?

Not being an expert in FIFO design, as I understand it in any
asynchronous system you have to assume that setup+hold won't always
be met. In crossing clock domains, either the signal will come
before the clock (and the operation will be performed) or it will
come after (and not be performed). If it comes after the clock,
then the operation is performed on the next clock cycle.

For FIFOs that is sometimes done by passing a Gray counter output
across the clock domain, in which case either the old or new value
is received on the other side. Those are the only choices.

-- glen
From: firefox3107 on 1 Jul 2010 01:19
I'm concerned about metastability and oscillation and in this
application note the flags are not synchronized with 2 flipflops in
the new clock domain.
So I'm asking if this FIFO design is reliable?
From: d_s_klein on 1 Jul 2010 16:57
On Jun 30, 10:19 pm, firefox3107 <firefox3...(a)gmail.com> wrote:
> I'm concerned about metastability and oscillation and in this
> application note the flags are not synchronized with 2 flipflops in
> the new clock domain.
> So I'm asking if this FIFO design is reliable?

I have been told by several people (Xilinx FAEs and Xilinx Users) that
the only reliable 2-clock FIFOs are the one created by coregen.

My understanding is that there is some magic (RPMs?) in the macro that
"just work".

My guess is that if you really choose to use this XAPP, you get to
verify it yourself (and re-verify it every time the placement
changes).

RK
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