Prev: RfC: Medical Software Task Force
Next: How to "su" WITHOUT changing the current directory?
From: annalissa on 18 Jul 2010 03:26
Hi all,

I tried to get cache information on my machine as follows

getconf -a | grep -i cache

zodiac(a)zodioc:~$ getconf -a | grep -i cache
LEVEL1_ICACHE_SIZE 32768
LEVEL1_ICACHE_ASSOC 8
LEVEL1_ICACHE_LINESIZE 64
LEVEL1_DCACHE_SIZE 32768
LEVEL1_DCACHE_ASSOC 8
LEVEL1_DCACHE_LINESIZE 64
LEVEL2_CACHE_SIZE 1048576
LEVEL2_CACHE_ASSOC 8
LEVEL2_CACHE_LINESIZE 64
LEVEL3_CACHE_SIZE 0
LEVEL3_CACHE_ASSOC 0
LEVEL3_CACHE_LINESIZE 0
LEVEL4_CACHE_SIZE 0
LEVEL4_CACHE_ASSOC 0
LEVEL4_CACHE_LINESIZE 0



does this listing means that LINESIZE of my L2 cache is 64 bytes and
that L2 cache is divided into units comprising of 8 cache lines(each
of 64 bytes in size) ?
From: Jeff Long on 19 Jul 2010 11:55
annalissa wrote:
> Hi all,
>
> I tried to get cache information on my machine as follows
>
> getconf -a | grep -i cache
>
> zodiac(a)zodioc:~$ getconf -a | grep -i cache
> LEVEL1_ICACHE_SIZE 32768
> LEVEL1_ICACHE_ASSOC 8
> LEVEL1_ICACHE_LINESIZE 64
> LEVEL1_DCACHE_SIZE 32768
> LEVEL1_DCACHE_ASSOC 8
> LEVEL1_DCACHE_LINESIZE 64
> LEVEL2_CACHE_SIZE 1048576
> LEVEL2_CACHE_ASSOC 8
> LEVEL2_CACHE_LINESIZE 64
> LEVEL3_CACHE_SIZE 0
> LEVEL3_CACHE_ASSOC 0
> LEVEL3_CACHE_LINESIZE 0
> LEVEL4_CACHE_SIZE 0
> LEVEL4_CACHE_ASSOC 0
> LEVEL4_CACHE_LINESIZE 0
>
>
>
> does this listing means that LINESIZE of my L2 cache is 64 bytes and
> that L2 cache is divided into units comprising of 8 cache lines(each
> of 64 bytes in size) ?

Almost right except for the associativity.
http://en.wikipedia.org/wiki/CPU_cache#Associativity seems to have an ok
defintion of it.

Jeff Long
From: annalissa on 20 Jul 2010 01:17
On Jul 19, 11:55 am, Jeff Long <long@[127.0.0.1]> wrote:
> annalissa wrote:
> > Hi all,
>
> > I tried to get cache information on my machine as follows
>
> > getconf -a | grep -i cache
>
> > zodiac(a)zodioc:~$ getconf -a | grep -i cache
> > LEVEL1_ICACHE_SIZE 32768
> > LEVEL1_ICACHE_ASSOC 8
> > LEVEL1_ICACHE_LINESIZE 64
> > LEVEL1_DCACHE_SIZE 32768
> > LEVEL1_DCACHE_ASSOC 8
> > LEVEL1_DCACHE_LINESIZE 64
> > LEVEL2_CACHE_SIZE 1048576
> > LEVEL2_CACHE_ASSOC 8
> > LEVEL2_CACHE_LINESIZE 64
> > LEVEL3_CACHE_SIZE 0
> > LEVEL3_CACHE_ASSOC 0
> > LEVEL3_CACHE_LINESIZE 0
> > LEVEL4_CACHE_SIZE 0
> > LEVEL4_CACHE_ASSOC 0
> > LEVEL4_CACHE_LINESIZE 0
>
> > does this listing means that LINESIZE of my L2 cache is 64 bytes and
> > that L2 cache is divided into units comprising of 8 cache lines(each
> > of 64 bytes in size) ?
>
> Almost right except for the associativity.http://en.wikipedia.org/wiki/CPU_cache#Associativityseems to have an ok
> defintion of it.
>
> Jeff Long


I found the following explanation here http://www.pcguide.com/ref/mbsys/cache/func.htm
:-

so what is wrong in my understanding ?


N-Way Set Associative Cache: "N" here is a number, typically 2, 4, 8
etc. This is a compromise between the direct mapped and fully
associative designs. In this case the cache is broken into sets where
each set contains "N" cache lines, let's say 4. Then, each memory
address is assigned a set, and can be cached in any one of those 4
locations within the set that it is assigned to. In other words,
within each set the cache is associative, and thus the name.
From: Jeff Long on 20 Jul 2010 12:31
annalissa wrote:
> On Jul 19, 11:55 am, Jeff Long<long@[127.0.0.1]> wrote:
>> annalissa wrote:

>>> LEVEL2_CACHE_SIZE 1048576
>>> LEVEL2_CACHE_ASSOC 8
>>> LEVEL2_CACHE_LINESIZE 64
>>> LEVEL3_CACHE_SIZE 0
>>> LEVEL3_CACHE_ASSOC 0
>>> LEVEL3_CACHE_LINESIZE 0
>>> LEVEL4_CACHE_SIZE 0
>>> LEVEL4_CACHE_ASSOC 0
>>> LEVEL4_CACHE_LINESIZE 0
>>
>>> does this listing means that LINESIZE of my L2 cache is 64 bytes and
>>> that L2 cache is divided into units comprising of 8 cache lines(each
>>> of 64 bytes in size) ?
>>
>> Almost right except for the associativity.http://en.wikipedia.org/wiki/CPU_cache#Associativityseems to have an ok
>> defintion of it.
>>
>> Jeff Long
>
>
> I found the following explanation here http://www.pcguide.com/ref/mbsys/cache/func.htm
> :-
>
> so what is wrong in my understanding ?
>
>
> N-Way Set Associative Cache: "N" here is a number, typically 2, 4, 8
> etc. This is a compromise between the direct mapped and fully
> associative designs. In this case the cache is broken into sets where
> each set contains "N" cache lines, let's say 4. Then, each memory
> address is assigned a set, and can be cached in any one of those 4
> locations within the set that it is assigned to. In other words,
> within each set the cache is associative, and thus the name.

yeah, true, guess that's another way of wording it

 | 
Pages: 1
Prev: RfC: Medical Software Task Force
Next: How to "su" WITHOUT changing the current directory?