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From: Eric Anholt on 22 Apr 2010 18:00 The following changes since commit 13bd8e4673d527a9e48f41956b11d391e7c2cfe0: Linus Torvalds (1): Merge branch 'for-linus' of git://git.kernel.org/.../anholt/drm-intel are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel for-linus I hear you've got an Ironlake laptop. If so, it's time to get excited. The interrupt wedging fix is here. The docs since the original gen4 have said "stop using MI_STORE_DWORD_INDEX+MI_USER_INTERRUPT, it's not guaranteed to be ordered, so use the fancy new PIPE_CONTROL." I was thinking that ignoring this might be the problem with our interrupts. So jbarnes tried it, and it made things hang even faster. Then Zhenyu found an errata: Pipe control doesn't have working ordering on Ironlake, so do it twice, with 6 dummy PIPE_CONTROLs in between. GPUs are awesome. Adam Jackson (2): drm/i915: Attempt to fix watermark setup on 85x (v2) drm/i915: Fix 82854 PCI ID, and treat it like other 85X Daniel Vetter (1): drm/i915: fix tiling limits for i915 class hw v2 Jesse Barnes (2): drm/i915: cleanup FBC buffers at unload time drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge Zhang Rui (1): drm/i915: set DIDL using the ACPI video output device _ADR method return. drivers/gpu/drm/i915/i915_dma.c | 14 +++ drivers/gpu/drm/i915/i915_drv.c | 5 +- drivers/gpu/drm/i915/i915_drv.h | 10 ++- drivers/gpu/drm/i915/i915_gem.c | 151 +++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_gem_tiling.c | 22 ++--- drivers/gpu/drm/i915/i915_irq.c | 8 +- drivers/gpu/drm/i915/i915_opregion.c | 54 +++++++++++- drivers/gpu/drm/i915/i915_reg.h | 13 +++- drivers/gpu/drm/i915/intel_display.c | 11 ++- 9 files changed, 246 insertions(+), 42 deletions(-) |