infering BRAM for a FIFO in XST(spartan 3)
in [FPGA]
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From: PureSine on 29 Mar 2010 12:43 Hello, I want to tell XST that uses block RAM for my FIFO, but I couldn't till now. can you please take a look at my code and tell me what should I do ? http://openpaste.org/en/20191/ thanks
From: Patrick Maupin on 29 Mar 2010 17:26 On Mar 29, 11:43 am, PureSine <Green.Tech.Co...(a)gmail.com> wrote: > Hello, I want to tell XST that uses block RAM for my FIFO, > but I couldn't till now. can you please take a look at my > code and tell me what should I do ?http://openpaste.org/en/20191/ > > thanks I'm not looking at your code right now, but I will tell you how to fix it. Start with one of the BRAM examples in Xilinx's XST guide. Make sure that when you synthesize it, it generates a block ram. Munge on it until the I/Os to the module look like what you want (resynthesizing as you go to insure you haven't done anything to make XST think it's not a synchronous block ram any more). Then build your FIFO wrapper around it. BTW, if you are building a synchronous FIFO where both input and output are on the same clock, some of the xilinx tools get pissy if you don't declare the two ports to the RAM in two different processes. That can be a problem, because you can have a design that is logically correct for a block ram, but won't infer as one. That's why the best approach is to incrementally modify a working design -- the synthesis tools are a little fragile on the whole inference thing. Alternatively, you could just instantiate the block ram, but I prefer not to do that if I don't have to, since if it's inferred I can simulate it with anything. Regards, Pat
From: PureSine on 29 Mar 2010 21:56 On 3/30/2010 1:56 AM, Patrick Maupin wrote: > On Mar 29, 11:43 am, PureSine<Green.Tech.Co...(a)gmail.com> wrote: >> Hello, I want to tell XST that uses block RAM for my FIFO, >> but I couldn't till now. can you please take a look at my >> code and tell me what should I do ?http://openpaste.org/en/20191/ >> >> thanks > > I'm not looking at your code right now, but I will tell you how to fix > it. > > Start with one of the BRAM examples in Xilinx's XST guide. Make sure > that when you synthesize it, it generates a block ram. Munge on it > until the I/Os to the module look like what you want (resynthesizing > as you go to insure you haven't done anything to make XST think it's > not a synchronous block ram any more). Then build your FIFO wrapper > around it. > > BTW, if you are building a synchronous FIFO where both input and > output are on the same clock, some of the xilinx tools get pissy if > you don't declare the two ports to the RAM in two different > processes. That can be a problem, because you can have a design that > is logically correct for a block ram, but won't infer as one. That's > why the best approach is to incrementally modify a working design -- > the synthesis tools are a little fragile on the whole inference thing. > > Alternatively, you could just instantiate the block ram, but I prefer > not to do that if I don't have to, since if it's inferred I can > simulate it with anything. > > > Regards, > Pat Thanks a lot Pat :) , I will try and if I had problem I'll post it here. Regards
From: PureSine on 29 Mar 2010 22:49 On 3/30/2010 1:56 AM, Patrick Maupin wrote: > On Mar 29, 11:43 am, PureSine<Green.Tech.Co...(a)gmail.com> wrote: >> Hello, I want to tell XST that uses block RAM for my FIFO, >> but I couldn't till now. can you please take a look at my >> code and tell me what should I do ?http://openpaste.org/en/20191/ >> >> thanks > > I'm not looking at your code right now, but I will tell you how to fix > it. > > Start with one of the BRAM examples in Xilinx's XST guide. Make sure > that when you synthesize it, it generates a block ram. Munge on it > until the I/Os to the module look like what you want (resynthesizing > as you go to insure you haven't done anything to make XST think it's > not a synchronous block ram any more). Then build your FIFO wrapper > around it. > > BTW, if you are building a synchronous FIFO where both input and > output are on the same clock, some of the xilinx tools get pissy if > you don't declare the two ports to the RAM in two different > processes. That can be a problem, because you can have a design that > is logically correct for a block ram, but won't infer as one. That's > why the best approach is to incrementally modify a working design -- > the synthesis tools are a little fragile on the whole inference thing. > > Alternatively, you could just instantiate the block ram, but I prefer > not to do that if I don't have to, since if it's inferred I can > simulate it with anything. > > > Regards, > Pat Thanks Pat :) , that worked. Now I have a BRAM FIFO. Thanks for your help. Regards
From: Patrick Maupin on 29 Mar 2010 23:48 On Mar 29, 9:49 pm, PureSine <Green.Tech.Co...(a)gmail.com> wrote: > Thanks Pat :) , that worked. Now I have a BRAM FIFO. > Thanks for your help. You're welcome! Glad you got it working. Pat
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