manual Route before PAR starts in xilinx ISE 12
in [FPGA]
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From: Amish Rughoonundon on 12 Jul 2010 11:32 Hi, I have a design that use some asynchronous signals. I have already set a FROM TO constraint in the ucf for the path. I am using a Spartan 3E 1600-5fg400 with Xilinx ISE 12 on top of that, I located the optimum path that the signal should take on the chip. If I let PAR run automatically, it does not map it on that path. I would like to know if there is a way that I can tell PAR that this signal has the highest priority and that it should route it first before routing anything else. Alternatively, is there a way I can manually set the route. I have done this before under "map -> Manually place and route" but when PAR runs, it remaps it. I would like a way to set it so that if the project is cleaned up using "project->clean project files", the manual route is not erased. It's hard to explain. Hopefully somebody has done this before. Thanks a lot, Amish
From: John McCaskill on 12 Jul 2010 12:36 On Jul 12, 10:32 am, Amish Rughoonundon <amishrughoonun...(a)gmail.com> wrote: > Hi, > I have a design that use some asynchronous signals. I have already > set a FROM TO constraint in the ucf for the path. > > I am using a Spartan 3E 1600-5fg400 with Xilinx ISE 12 > > on top of that, I located the optimum path that the signal should take > on the chip. > > If I let PAR run automatically, it does not map it on that path. > > I would like to know if there is a way that I can tell PAR that this > signal has the highest priority and that it should route it first > before routing anything else. > > Alternatively, is there a way I can manually set the route. I have > done this before under "map -> Manually place and route" but when PAR > runs, it remaps it. > > I would like a way to set it so that if the project is cleaned up > using "project->clean project files", the manual route is not erased. > > It's hard to explain. Hopefully somebody has done this before. > > Thanks a lot, > Amish Hello Amish, Yes, it is possible to manually place and route a signal, and then put that information into the UCF file so you only have to do it once. I have done it, but only as a last resort. Can you tell us a bit about what you are trying to do with the asynchronous signals that needs this sort of placement? There may be a better way to accomplish your goal. If you really want to hand route the signals, use the design in FPGA Editor and set the edit mode to read/write. Select the net to route, and unroute it. Reroute it by hand. Then select Directed Routing Constraints from the Tools menu. This will bring up a new window that will let you select the nets you are interested in and will create placement and routing constraints that you can put into the UCF for the design. After that, these constraints will cause the tools to replicate the routing every time you run place and route. Regards, John McCaskill www.FasterTechnology.com
From: Amish Rughoonundon on 12 Jul 2010 13:40 On Jul 12, 12:36 pm, John McCaskill <jhmccask...(a)gmail.com> wrote: > On Jul 12, 10:32 am, Amish Rughoonundon <amishrughoonun...(a)gmail.com> > wrote: > > > > > > > Hi, > > I have a design that use some asynchronous signals. I have already > > set a FROM TO constraint in the ucf for the path. > > > I am using a Spartan 3E 1600-5fg400 with Xilinx ISE 12 > > > on top of that, I located the optimum path that the signal should take > > on the chip. > > > If I let PAR run automatically, it does not map it on that path. > > > I would like to know if there is a way that I can tell PAR that this > > signal has the highest priority and that it should route it first > > before routing anything else. > > > Alternatively, is there a way I can manually set the route. I have > > done this before under "map -> Manually place and route" but when PAR > > runs, it remaps it. > > > I would like a way to set it so that if the project is cleaned up > > using "project->clean project files", the manual route is not erased. > > > It's hard to explain. Hopefully somebody has done this before. > > > Thanks a lot, > > Amish > > Hello Amish, > > Yes, it is possible to manually place and route a signal, and then put > that information into the UCF file so you only have to do it once. I > have done it, but only as a last resort. > > Can you tell us a bit about what you are trying to do with the > asynchronous signals that needs this sort of placement? There may be a > better way to accomplish your goal. > > If you really want to hand route the signals, use the design in FPGA > Editor and set the edit mode to read/write. Select the net to route, > and unroute it. Reroute it by hand. Then select Directed Routing > Constraints from the Tools menu. This will bring up a new window that > will let you select the nets you are interested in and will create > placement and routing constraints that you can put into the UCF for > the design. > > After that, these constraints will cause the tools to replicate the > routing every time you run place and route. > > Regards, > > John McCaskillwww.FasterTechnology.com Thanks for the quick answer. It seems to work now. This is what I am trying to route. I need the fastest possible response time under 5 ns. dsp_ms_three_n is an external signal to the chip s_done comes from a state machine running at 102.4 MHz which is also the clock rate for the communication to a dsp actuating dsp_ms_three_n [CODE] -- ACKNOWLEGEMENT -- -- Intentional latch created to obtain -- the fastest response time possible -- p_doneLatch : process(s_done, dsp_ms_three_n) begin if(s_done = '1') then s_doneLatch <= '1'; elsif(dsp_ms_three_n = '0') then s_doneLatch <= '0'; end if; end process p_doneLatch; dsp_ack <= 'Z' when dsp_ms_three_n = '1' else s_doneLatch; [/CODE] I am not sure how to do this synchornously with incurring the additional clock cycle and having to add double buffers on ms_three_n Amish
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