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From: austin on 12 Nov 2009 10:22 nishad, Why do you doubt? If the data sheet says an IO may sink 8 mA, then why not ALL IO at 8 mA? No problem. The only concern here is ground/Vcc bounce: yes, 128 * 8mA is a lot of current, and you should make sure your pcb has good power and ground planes, and the recommended bypass capacitors. Austin
From: Gabor on 12 Nov 2009 11:08 On Nov 12, 10:22 am, austin <aus...(a)xilinx.com> wrote: > nishad, > > Why do you doubt? If the data sheet says an IO may sink 8 mA, then > why not ALL IO at 8 mA? > > No problem. > > The only concern here is ground/Vcc bounce: yes, 128 * 8mA is a lot > of current, and you should make sure your pcb has good power and > ground planes, and the recommended bypass capacitors. > > Austin On the other hand if you really need 120 I/O's you may want to consider breaking it up into two packages. It might even save board area over one very large package. Of course that depends on how may additional pins you use to split the design in two. Sometimes it comes almost free, for example a two-wire serial bus. 1 Amp of switching current in a large PQFP results in lots of ground and Vcc bounce due to the large package lead inductance. Generally speaking, when using quad flat packs, the smaller the better because the die size of the chip inside gets closer to the overall package size as you get smaller, so the lead inductance is smaller, too. I'm not sure how it works with mature CPLD devices, but for FPGA's at least the price per I/O is better in smaller devices as well. Regards, Gabor
From: -jg on 12 Nov 2009 16:56 On Nov 13, 2:08 am, "nishad" <abnis...(a)gmail.com> wrote: > My requirement is to replace fifteen 7 segment display drivers using cpld > logic. > Total I/O connected to display will be 15*8=120. > Each pin has to sink around 8mA, so Im planning to go for Xilinx XC95288XL > CPLD. > My doubt is that can the cpld sink 120 lines of 8mA simultaneously? A XC95288XLis an expensive shift register ? :) or is it doing other things as well ? LED drive is generally better done with smaller, daisy chained CPLDs, or even just shift registers. -jg
From: nishad on 12 Nov 2009 23:03 >nishad, > >Why do you doubt? If the data sheet says an IO may sink 8 mA, then >why not ALL IO at 8 mA? > >No problem. > >The only concern here is ground/Vcc bounce: yes, 128 * 8mA is a lot >of current, and you should make sure your pcb has good power and >ground planes, and the recommended bypass capacitors. > >Austin > Thanks a lot for the reply... --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
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