problem in clock input in virtexpro/spartan3a/spartan3 kit
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From: varun_agr on 13 May 2010 15:30 hi In virtexpro/spartan3a/spartan3 kit when we using system clock(100Mz/50Mhz) and take this clock on i/o pin(by writing VHDL program) on digital C.R.O. it will show corrupred signal , I also tried this by DCM CORE GENERATOR again it is giving wrong o/p. Can anybody suggested me solution of this problem. --------------------------------------- Posted through http://www.FPGARelated.com
From: Ed McGettigan on 13 May 2010 19:06 On May 13, 12:30 pm, "varun_agr" <VARUN_AGR(a)n_o_s_p_a_m.YAHOO.COM> wrote: > hi > In virtexpro/spartan3a/spartan3 kit when we using system clock(100Mz/50Mhz) > and take this clock on i/o pin(by writing VHDL program) on digital C.R.O. > it will show corrupred signal , I also tried this by DCM CORE GENERATOR > again it is giving wrong o/p. Can anybody suggested me solution of this > problem. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com Based on your post you have the exact same behaviour on three different families, Virtex-II Pro, Spartan-3A and Spartan-3. This is strong indication that physical implementions are an exact match with the VHDL code that you wrote. Since you never indicated what your intended output was, what the output actually appears as nor the VHDL code it is unlikely that anyone can help you. Ed McGettigan -- Xilinx Inc.
From: jt_eaton on 13 May 2010 23:17 >hi >In virtexpro/spartan3a/spartan3 kit when we using system clock(100Mz/50Mhz) >and take this clock on i/o pin(by writing VHDL program) on digital C.R.O. >it will show corrupred signal , I also tried this by DCM CORE GENERATOR >again it is giving wrong o/p. Can anybody suggested me solution of this >problem. > > > >--------------------------------------- >Posted through http://www.FPGARelated.com > How are you measuring this? scope? probe? analyzer? Try dividing it down by 100 and see if you can measure that. What is you pad drive current set to? --------------------------------------- Posted through http://www.FPGARelated.com
From: Andy Peters on 14 May 2010 18:37
On May 13, 8:17 pm, "jt_eaton" <z3qmtr45(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >hi > >In virtexpro/spartan3a/spartan3 kit when we using system > clock(100Mz/50Mhz) > >and take this clock on i/o pin(by writing VHDL program) on digital C.R.O.. > >it will show corrupred signal , I also tried this by DCM CORE GENERATOR > >again it is giving wrong o/p. Can anybody suggested me solution of this > >problem. > > >--------------------------------------- > >Posted throughhttp://www.FPGARelated.com > > How are you measuring this? scope? probe? analyzer? He said "digital C.R.O." Funny, my digital scope does not have a cathode ray tube! -a |