problems with verilog SDRAM models
in [FPGA]
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From: Niv on 28 Nov 2006 06:20 wallge wrote: > I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanks Hi, I'm trying to use an AMD (Spansion) FLASH model, and it's just one BIG headache. Despite following all their advice and recompiling lots of libraries with vital2000, the model still falls over immediately in modelsim. It's really poor putting out models that just don't work, IMO. Kev P.
From: Brian Drummond on 28 Nov 2006 08:24 On 27 Nov 2006 14:54:21 -0800, "wallge" <wallge(a)gmail.com> wrote: >I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM >that I want to be able to control via an FPGA on the same PCB. >I am having trouble with the verilog model. I have used both a samsung >and a micron model for the part (two compatible parts). Unfortunately >these models are not available in VHDL, and my verilog is pretty weak. Micron certainly used to provide good VHDL models, and I wish they still did. Look for an older non-mobile equivalent for the SDRAM (same size, bus width, banks, etc and same speed grade if possible) and you'll probably find a VHDL model for it. Failing that, Hynix provide VHDL models, but I don't know if they have an equivalent part to the mobile SDRAM you are using. - Brian
From: FMF on 2 Dec 2006 23:45 Kev, Please contact me through the FMF website. We have received no bug reports on this model. Although the VITAL2000 issue is common, it is limited to modelsim. I will help you workout whatever other issues you have. If there is an actual bug, we are under contract from Spansion to fix it. Rick Munden Niv wrote: > wallge wrote: >> I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM >> that I want to be able to control via an FPGA on the same PCB. >> I am having trouble with the verilog model. I have used both a samsung >> and a micron model for the part (two compatible parts). Unfortunately >> these models are not available in VHDL, and my verilog is pretty weak. >> >> I wondered if any one had some experience with memory models, both in >> terms of using them to design memory controllers and debugging them >> when they spit out spurious timing violations. >> These verilog models in particular seem to send out all manner of >> timing violations or functional problems that don't seem to be in line >> at all with what the data sheet says regarding the timing and command >> and control procedures (for doing a full page read or write, for >> instance). >> >> Has any one else had trouble with bad/buggy models? What is the best >> way to solve this problem? >> What is the best way to go about designing a memory controller (I have >> seen an example on Altera's website in VHDL (but it sucks), as well as >> some others in open cores and one written for a homebrew graphics >> accelerator card (manticore). I find the documentation and/or >> functionality lacking in most of the aforementioned existing reference >> designs. >> >> thanks > > Hi, I'm trying to use an AMD (Spansion) FLASH model, and it's just one > BIG headache. > Despite following all their advice and recompiling lots of libraries > with vital2000, the model > still falls over immediately in modelsim. > > It's really poor putting out models that just don't work, IMO. > > Kev P. >
From: FMF on 2 Dec 2006 23:47 What partnumber do you need to simulate? wallge wrote: > I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanks >
From: Kevin Neilson on 4 Dec 2006 13:27
wallge wrote: > I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. .... I used a Verilog Micron model to develop my DDR/DDR2 controller and was very happy with the model. I had to set a couple of `defparams to make the model match my hardware, and it was very helpful in reporting all timing errors, such as violations in write recovery time, etc. There is a "Debug" parameter you can switch on to report all data transactions as well. Before you write your own controller, though, I warn you that it is much more difficult than you anticipate. -Kevin |