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From: jogendersaini on 9 May 2010 12:04
Hello,

I am working on Vertex-5 and i have made a 20-bit counter.

i have taken

signal counter : std_logic_vector (19 downto 0)

Output of the counter is monitored on scope with pre-specified pins. But
surprisingly the output is first 8-bit showing proper counting and next
8-bit is similar to 1st 8-bit and last 4-bit is showing output 0. This is
very strange. I dont konw common or uncommon mistake i have done.



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From: KJ on 9 May 2010 18:26
On May 9, 12:04 pm, "jogendersaini"
<jogendra.saini(a)n_o_s_p_a_m.gmail.com> wrote:
> Hello,
>
> I am working on Vertex-5 and i have made a 20-bit counter.
>
> i have taken
>
> signal counter : std_logic_vector (19 downto 0)
>
> Output of the counter is monitored on scope with pre-specified pins. But
> surprisingly the output is first 8-bit showing proper counting and next
> 8-bit is similar to 1st 8-bit and last 4-bit is showing output 0. This is
> very strange. I dont konw common or uncommon mistake i have done.
>

1. Simulate your design until you can show that the design is
functionally correct.
2. Perform timing analysis until you can show that the design has no
timing errors.
3. Watch the scope show that everything is now working as you'd
expect.

KJ
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