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From: Symon on 20 Feb 2010 12:21
On 2/19/2010 7:58 PM, Marcelo wrote:
> Ed,
> So you told me that its no posible to sent two bits using diferent MGT with the same delay?
> But how work the comm systems that use several paralle channels?

http://en.wikipedia.org/wiki/XAUI
From: marcelo on 21 Feb 2010 21:03
yes I understand but 500ps is to much for pcb delay, are 15cm.
The idia is ti desing an ultra wideband transmiter using the MGT.
I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo pulse), must be the same.


---
frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1
From: Ed McGettigan on 22 Feb 2010 00:00
On Feb 19, 11:58 am, Marcelo <u...(a)compgroups.net/> wrote:
> Ed,
> So you told me that its no posible to sent two bits using diferent MGT with the same delay?
> But how work the comm systems that use several paralle channels?
> I'll check the datasheet for my virtex2p.
> Marcelo
>
> ---
> frmsrcurl:http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-...

For interfaces that use multiple MGTs, such as PCIe and XAUI, the
protocol uses channel bonding that allows the receiver to align the
data correctly with multiple (1-40+) bits of skew. The are some
standards that want to skimp on the logic resources needed to
implement channel bonding and have a tighter requirement on the lane
skew, but the protocols that I am aware of still allow for about
1000pS of lane skew.

Expecting 0pS of lane skew is not realistic.

Ed McGettigan
--
Xilinx Inc.
From: Symon on 22 Feb 2010 05:18
On 2/22/2010 2:03 AM, marcelo wrote:
> yes I understand but 500ps is to much for pcb delay, are 15cm.
> The idia is ti desing an ultra wideband transmiter using the MGT.
> I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo pulse), must be the same.
>
>
> ---
> frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

Do you remember this reply from a week ago?


"What are these two signals? Where do they connect to your FPGA?"


Why don't you answer it?

Symon.
From: Symon on 22 Feb 2010 05:56
On 2/22/2010 10:18 AM, Symon wrote:
> On 2/22/2010 2:03 AM, marcelo wrote:
>> yes I understand but 500ps is to much for pcb delay, are 15cm.
>> The idia is ti desing an ultra wideband transmiter using the MGT.
>> I'm using BPKS modulation, so the delay between TX1(positive pulse)
>> and TX2(negativo pulse), must be the same.
>>
>>
>> ---
>> frmsrcurl:
>> http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1
>>
>
> Do you remember this reply from a week ago?
>
>
> "What are these two signals? Where do they connect to your FPGA?"
>
>
> Why don't you answer it?
>
> Symon.

Sorry, ignore that. I thought you were the OP. FWIW, the P and N signals
will be aligned to within a few ps. Different lanes will not be.

HTH,

Syms.
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