simulating a digital control loop
in [Design]
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From: Peter Way on 17 Apr 2010 19:40 You can simulate the analog, digital, or hybrid control loops with SimApp www.simapp.com These can be done in a simple block diagram form. Peter www.ventimar.com
From: John Larkin on 17 Apr 2010 20:36 On Mon, 29 Mar 2010 19:59:56 +0200, "Helmut Sennewald" <helmutsennewald(a)t-online.de> wrote: >> .. >> I can simulate it as an analog loop using LT Spice, as I'm familiar >> with that and could get it done quickly. It would be handy if I could >> also use the same model in digital mode, which would add sampling >> delays and maybe even quantization. >> >> Any thoughts on how to do this? >> ... >> John > >Hello John, > >LTspice has a sample/hold device. >It's named "sample" and you can get it from [Special Functions]. >It allows to sample and hold a signal with the edge of a clock signal. >Additional B-sources can be used to do the math in the loop. >Even quantization is possible with the help of int() functions in >the B-sources. > >Best regards, >Helmut > How do I make a schematic symbol, a B-source I guess, that's essentially a VCVS with my equation inside it? There's an int() function available for use in equations, so quantization looks pretty easy... scale up, int, scale back down. The HELP is just not specific on how to hook it all up. Anybody got an example? John
From: Helmut Sennewald on 18 Apr 2010 07:27 "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> schrieb im Newsbeitrag news:ahkks55rddd5prf0570plnqr0vj3ndtnna(a)4ax.com... > On Mon, 29 Mar 2010 19:59:56 +0200, "Helmut Sennewald" > <helmutsennewald(a)t-online.de> wrote: > >>> .. >>> I can simulate it as an analog loop using LT Spice, as I'm familiar >>> with that and could get it done quickly. It would be handy if I could >>> also use the same model in digital mode, which would add sampling >>> delays and maybe even quantization. >>> >>> Any thoughts on how to do this? >>> ... >>> John >> >>Hello John, >> >>LTspice has a sample/hold device. >>It's named "sample" and you can get it from [Special Functions]. >>It allows to sample and hold a signal with the edge of a clock signal. >>Additional B-sources can be used to do the math in the loop. >>Even quantization is possible with the help of int() functions in >>the B-sources. >> >>Best regards, >>Helmut >> > > How do I make a schematic symbol, a B-source I guess, that's > essentially a VCVS with my equation inside it? There's an int() > function available for use in equations, so quantization looks pretty > easy... scale up, int, scale back down. The HELP is just not specific > on how to hook it all up. > > Anybody got an example? > > John Hello John, Here is an example. Best regards, Helmut Version 4 SHEET 1 1268 1716 WIRE -960 -256 -992 -256 WIRE -432 -256 -464 -256 WIRE -992 -224 -992 -256 WIRE -464 -224 -464 -256 WIRE -992 -112 -992 -144 WIRE -464 -112 -464 -144 WIRE -464 -16 -480 -16 WIRE -1568 32 -1600 32 WIRE -1232 32 -1264 32 WIRE -992 32 -1024 32 WIRE -864 32 -912 32 WIRE -752 32 -864 32 WIRE -480 32 -480 -16 WIRE -80 32 -480 32 WIRE -64 32 -80 32 WIRE -1600 64 -1600 32 WIRE -1264 64 -1264 32 WIRE -864 64 -864 32 WIRE -480 64 -480 32 WIRE -64 64 -64 32 WIRE -528 80 -576 80 WIRE -752 96 -784 96 WIRE -864 160 -864 128 WIRE -1600 176 -1600 144 WIRE -1264 176 -1264 144 WIRE -528 176 -528 128 WIRE -480 176 -480 144 WIRE -64 176 -64 144 WIRE -1200 272 -1264 272 WIRE -1264 304 -1264 272 WIRE -208 320 -272 320 WIRE -64 320 -128 320 WIRE -64 352 -64 320 WIRE -512 368 -544 368 WIRE -272 368 -272 320 WIRE -1264 416 -1264 384 WIRE -720 416 -752 416 WIRE -512 432 -544 432 WIRE -272 464 -272 448 WIRE -64 464 -64 416 FLAG -528 176 0 FLAG -960 -256 target IOPIN -960 -256 Out FLAG -992 -112 0 FLAG -1264 416 0 FLAG -1200 272 IE IOPIN -1200 272 Out FLAG -480 176 0 FLAG -64 176 0 FLAG -64 464 0 FLAG -272 464 0 FLAG -80 32 VRL FLAG -64 320 VT FLAG -512 368 VT FLAG -512 432 clk FLAG -1600 176 0 FLAG -1568 32 E1 IOPIN -1568 32 Out FLAG -784 96 clk FLAG -752 416 ACTUAL IOPIN -752 416 Out FLAG -1264 176 0 FLAG -1232 32 ER IOPIN -1232 32 Out FLAG -432 -256 clk IOPIN -432 -256 Out FLAG -464 -112 0 FLAG -1024 32 ER FLAG -864 160 0 FLAG -464 -16 DRIVE IOPIN -464 -16 Out SYMBOL e -480 48 R0 SYMATTR InstName E1 SYMATTR Value 1 SYMBOL voltage -992 -240 R0 WINDOW 3 25 91 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 20 5.1 1n 1n 50 100) SYMATTR InstName V3 SYMBOL bv -1264 288 R0 SYMATTR InstName B1 SYMATTR Value V=idt(K2*V(E1)/PERIOD) SYMBOL res -80 48 R0 SYMATTR InstName RL SYMATTR Value 1 SYMBOL bv -272 352 R0 WINDOW 3 -15 164 Left 0 SYMATTR InstName B11 SYMATTR Value V=sgn(V(VRL))*10*V(VRL)*I(RL) SYMBOL res -224 336 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName RT SYMATTR Value 1k SYMBOL cap -80 352 R0 SYMATTR InstName CT SYMATTR Value 10m SYMBOL SpecialFunctions\\sample -624 400 M0 WINDOW 39 -100 129 Left 0 SYMATTR InstName A3 SYMATTR SpiceLine Vhigh=100 Vlow=-100 SYMBOL bv -1600 48 R0 SYMATTR InstName B7 SYMATTR Value V=(V(Target)-V(Actual)) SYMBOL SpecialFunctions\\sample -672 64 R0 WINDOW 39 -77 128 Left 0 SYMATTR InstName A1 SYMATTR SpiceLine Vhigh=4 Vlow=-4 SYMBOL bv -1264 48 R0 SYMATTR InstName B12 SYMATTR Value V=K1*V(E1)+V(IE) SYMBOL voltage -464 -240 R0 WINDOW 3 25 91 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 1 0 1n 1n {PERIOD/2} {PERIOD}) SYMATTR InstName V1 SYMBOL cap -880 64 R0 WINDOW 3 -57 141 Left 0 SYMATTR InstName C1 SYMATTR Value {PERIOD*.1u} SYMBOL res -1008 48 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 1k TEXT -1608 -240 Left 0 !.tran 0 100 0 10m TEXT -1608 -208 Left 0 !.param PERIOD=0.1 TEXT -1184 312 Left 0 ;Integral TEXT -640 288 Right 0 ;ADC TEXT -688 -32 Left 0 ;DAC TEXT -1000 -24 Left 0 ;hold time TEXT -1280 -8 Left 0 ;Regulator TEXT -1616 -8 Left 0 ;Target-Actual TEXT -256 248 Left 0 ;TEC Temperature TEXT -192 -16 Left 0 ;TEC TEXT -1272 -296 Left 0 ;TEC-Controller TEXT -1312 -144 Left 0 !* PI(D) parameters\n.param K1=0.5\n.param K2=20m RECTANGLE Normal 96 560 -336 -48
From: John Larkin on 18 Apr 2010 11:29 On Sun, 18 Apr 2010 13:27:25 +0200, "Helmut Sennewald" <helmutsennewald(a)t-online.de> wrote: > >"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> schrieb im >Newsbeitrag news:ahkks55rddd5prf0570plnqr0vj3ndtnna(a)4ax.com... >> On Mon, 29 Mar 2010 19:59:56 +0200, "Helmut Sennewald" >> <helmutsennewald(a)t-online.de> wrote: >> >>>> .. >>>> I can simulate it as an analog loop using LT Spice, as I'm familiar >>>> with that and could get it done quickly. It would be handy if I could >>>> also use the same model in digital mode, which would add sampling >>>> delays and maybe even quantization. >>>> >>>> Any thoughts on how to do this? >>>> ... >>>> John >>> >>>Hello John, >>> >>>LTspice has a sample/hold device. >>>It's named "sample" and you can get it from [Special Functions]. >>>It allows to sample and hold a signal with the edge of a clock signal. >>>Additional B-sources can be used to do the math in the loop. >>>Even quantization is possible with the help of int() functions in >>>the B-sources. >>> >>>Best regards, >>>Helmut >>> >> >> How do I make a schematic symbol, a B-source I guess, that's >> essentially a VCVS with my equation inside it? There's an int() >> function available for use in equations, so quantization looks pretty >> easy... scale up, int, scale back down. The HELP is just not specific >> on how to hook it all up. >> >> Anybody got an example? >> >> John > >Hello John, > >Here is an example. > >Best regards, >Helmut > Thanks, Helmut. LT Spice could use a few more examples, to make it easier for the occasional user. I figured out a quantizer separately, and posted it yesterday. I'll stick s/h boxes and quantizers (simulating 12 bit ADCs, 10 bit DAC) into my control loop and see if it gets weird. John
From: Tim Wescott on 18 Apr 2010 15:19
Peter Way wrote: > You can simulate the analog, digital, or hybrid control loops with > SimApp www.simapp.com > > These can be done in a simple block diagram form. But can you drop a circuit into it, and simulate that in a "spice-like" way while simulating the rest in a more abstract way? It's what John's looking for, and I know it's something that I'd find pretty darned useful. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com |