sqrt(a^2 + b^2) in synthesizable VHDL?
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From: Symon on 11 May 2006 04:56 "Michael Sch?berl" <MSchoeberl(a)mailtonne.de> wrote in message news:4462f354$1(a)news.fhg.de... > Marko S schrieb: >> How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? >> The signals a and b are 32 bit signed fix point numbers (std_logic_vector >> (31 downto 0)). > > how accurate? how fast? latency? > > just for the sqrt(x) I once worked an idea to take len=ceil(log_2(x)) by > counting the length of x (leading 0s) ... > then you shift x>>(len/2) or something (+1?) ... this worked as a good > approximation and I added only one or two stages of a newton-raphson > Hi Marko, For square root, you could use modified Dijkstra's square root. http://lib.tkk.fi/Diss/2005/isbn9512275279/article3.pdf One clock per output bit. No multipliers. HTH, Syms.
From: Marko S on 11 May 2006 05:58 Thank you all. I will have a look at "Dijkstra's square root". I have 2000 clock cycles at 40 Mhz to complete the calculation (It should be enough). It is used for calculating the AM envelop after demodulating the signal with a coherent detector You can se the principle of the detector at http://www.cycom.co.uk/art1.html. "Symon" <symon_brewer(a)hotmail.com> wrote in message news:4462fbb4$0$15793$14726298(a)news.sunsite.dk... > "Michael Sch?berl" <MSchoeberl(a)mailtonne.de> wrote in message > news:4462f354$1(a)news.fhg.de... >> Marko S schrieb: >>> How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? >>> The signals a and b are 32 bit signed fix point numbers >>> (std_logic_vector (31 downto 0)). >> >> how accurate? how fast? latency? >> >> just for the sqrt(x) I once worked an idea to take len=ceil(log_2(x)) by >> counting the length of x (leading 0s) ... >> then you shift x>>(len/2) or something (+1?) ... this worked as a good >> approximation and I added only one or two stages of a newton-raphson >> > Hi Marko, > For square root, you could use modified Dijkstra's square root. > > http://lib.tkk.fi/Diss/2005/isbn9512275279/article3.pdf > > One clock per output bit. No multipliers. > > HTH, Syms. >
From: Ray Andraka on 11 May 2006 13:27 Marko S wrote: > Thank you all. I will have a look at "Dijkstra's square root". I have 2000 > clock cycles at 40 Mhz to complete the calculation (It should be enough). It > is used for calculating the AM envelop after demodulating the signal with a > coherent detector > > > > You can se the principle of the detector at > http://www.cycom.co.uk/art1.html. > > > > > > "Symon" <symon_brewer(a)hotmail.com> wrote in message > news:4462fbb4$0$15793$14726298(a)news.sunsite.dk... > >>"Michael Sch?berl" <MSchoeberl(a)mailtonne.de> wrote in message >>news:4462f354$1(a)news.fhg.de... >> >>>Marko S schrieb: >>> >>>>How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? >>>>The signals a and b are 32 bit signed fix point numbers >>>>(std_logic_vector (31 downto 0)). >>> >>>how accurate? how fast? latency? >>> >>>just for the sqrt(x) I once worked an idea to take len=ceil(log_2(x)) by >>>counting the length of x (leading 0s) ... >>>then you shift x>>(len/2) or something (+1?) ... this worked as a good >>>approximation and I added only one or two stages of a newton-raphson >>> >> >>Hi Marko, >>For square root, you could use modified Dijkstra's square root. >> >>http://lib.tkk.fi/Diss/2005/isbn9512275279/article3.pdf >> >>One clock per output bit. No multipliers. >> >>HTH, Syms. >> > > > You aren't really looking for square root, you are looking for vector magnitude. Vector magnitude can be computed without computing the square root. For arbitrary precision, you can use the cordic algorithm in vectoring mode. It basically rotates the vector to the I axis using a series of progressively smaller fixed angle rotations selected so that each elemental rotation is done with a shift and add operation. After rotating the vector the I axis, the magnitude is read directly from the non-zero (I component) of the rotated vector. If you don't need a lot of precision, there are table methods and linear approximations (the most famous is "larger plus half smaller" that will often get you a good enough answer with less computation. Either way, computing magnitude using a square root is going about it the hard way (hardware-wise anyway). For 32 bit arguments, CORDIC is going to be your best bet.
From: gaurav.vaidya2000@gmail.com on 11 May 2006 17:03 If you are targetting programmable hardware (which you most possible are), you can get IP cores to work for you. Check out opencores.org or Xilinx or Altera websites to find cores that provide functions you need.
From: "jtw" <wrightjt on 11 May 2006 22:10 Do you need the square root, or can you work with just the "sum of the squares" (perhaps scaled)? If this is used for thresholding (amplitude comparison), then the less-than/equal/greater-than relationship still holds. JTW "Marko S" <someone(a)microsoft.com> wrote in message news:44630af8$0$15782$14726298(a)news.sunsite.dk... > Thank you all. I will have a look at "Dijkstra's square root". I have 2000 > clock cycles at 40 Mhz to complete the calculation (It should be enough). > It is used for calculating the AM envelop after demodulating the signal > with a coherent detector > > > > You can se the principle of the detector at > http://www.cycom.co.uk/art1.html. > > > > > > "Symon" <symon_brewer(a)hotmail.com> wrote in message > news:4462fbb4$0$15793$14726298(a)news.sunsite.dk... >> "Michael Sch?berl" <MSchoeberl(a)mailtonne.de> wrote in message >> news:4462f354$1(a)news.fhg.de... >>> Marko S schrieb: >>>> How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? >>>> The signals a and b are 32 bit signed fix point numbers >>>> (std_logic_vector (31 downto 0)). >>> >>> how accurate? how fast? latency? >>> >>> just for the sqrt(x) I once worked an idea to take len=ceil(log_2(x)) by >>> counting the length of x (leading 0s) ... >>> then you shift x>>(len/2) or something (+1?) ... this worked as a good >>> approximation and I added only one or two stages of a newton-raphson >>> >> Hi Marko, >> For square root, you could use modified Dijkstra's square root. >> >> http://lib.tkk.fi/Diss/2005/isbn9512275279/article3.pdf >> >> One clock per output bit. No multipliers. >> >> HTH, Syms. >> > >
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