temporal logic folding
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From: twospruces on 26 Jul 2010 10:04 all, I would like some feedback on a new FPGA architecture. Are there any serious configurable logic gurus on this group? If there is interest, I will post links to the 3 published papers that discuss in detail a logic architecture that offers better than 10x higher logic density than standard FPGA, along with a significant reduction in power. The research presents an architecture that can leverage "temporal logic folding". thanks.
From: Jonathan Bromley on 26 Jul 2010 16:52 On Mon, 26 Jul 2010 07:04:12 -0700 (PDT), twospruces wrote: >I would like some feedback on a new FPGA architecture. Are there any >serious configurable logic gurus on this group? I'm quite serious, and I'm highly configurable. Whether I'm a logic guru is entirely another matter :-) >If there is interest, I will post links to the 3 published papers that >discuss in detail a logic architecture that offers better than 10x >higher logic density than standard FPGA, along with a significant >reduction in power. If they are "published", in the sense that the information is in the public domain, then you have nothing to lose and all to gain: post the links anyway, and see if you get any bites. If they are under NDA or somesuch, then here is not the place. If you have published without speaking with a good patent lawyer, then your potential investors will likely not be very interested. >The research presents an architecture that can leverage "temporal >logic folding". That's kinda meaningless without the documentation. Is it anything like the stuff Tabula are doing? -- Jonathan Bromley
From: Frank Buss on 27 Jul 2010 16:37
Jonathan Bromley wrote: > That's kinda meaningless without the documentation. Is it > anything like the stuff Tabula are doing? I don't know. But searching for "temporal logic folding" results in this article (article creation date: august 2009) : http://mcwang.net/files/NATURE_Article.pdf Sounds interesting, but I guess it needs some more years of research before it is usable in a product and it doesn't help for all FPGA problems, because the space advantage has a speed penalty. -- Frank Buss, fb(a)frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de |