verilog multiplexer
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From: maxascent on 2 Jan 2010 05:27 >One of the simplest and most consistent multiplexers I've used is with >arrays of registers or wires. > >wire [p:0] my_sel; >wire [n:0] my_array [m:0]; // assign m+1 my_array values to the >desired inputs >reg [n:0] my_output; >// >always @(posedge clk) my_output <=3D my_array[my_sel]; > Thanks John that works great. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com |