wishbone
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From: LittleAlex on 19 Mar 2010 20:00 On Mar 19, 9:56 am, "HT-Lab" <han...(a)ht-lab.com> wrote: > > Depending on what you want to do with the core but I would suggest you also have > a look at the Amba bus since (thanks to Gaisler research?) this bus seems to be > gaining popularity amonst the space/mil-aero users. > > Hanswww.ht-lab.com > I have an objection to the AMBA bus. Namely: "This document is only available in a PDF version to registered ARM customers." Yuck.
From: HT-Lab on 20 Mar 2010 05:46 "LittleAlex" <alex.louie(a)email.com> wrote in message news:fc3e6150-3e2b-4e9e-8d99-99078be700d4(a)n39g2000prj.googlegroups.com... On Mar 19, 9:56 am, "HT-Lab" <han...(a)ht-lab.com> wrote: > > Depending on what you want to do with the core but I would suggest you also > have > a look at the Amba bus since (thanks to Gaisler research?) this bus seems to > be > gaining popularity amonst the space/mil-aero users. > > Hanswww.ht-lab.com > > >I have an objection to the AMBA bus. Namely: "This document is only >available in a PDF version to registered ARM customers." > >Yuck. There are lots of places were you can legally download it from, if you do a google search (amba bus protocol) then the first entry is wikipedia and the second is: http://ens.ewi.tudelft.nl/Education/courses/et4351/amba.pdf If you read the second page it states: Document confidentiality status This document is Open Access. This document has no restriction on distribution. Hans www.ht-lab.com
From: jt_eaton on 20 Mar 2010 10:10 >Hi everyone, >I'm just about to start an implementation of an open spacewire IP core >(still trying to understand under which license, GPL, LGPL, CeCILL...) >and I was wondering whether is a good idea to have a wishbone interface >implemented. >I am pretty new to SoC bus and even though google is "one of my best >friends" I still didn't get the feeling how popular it is and how spread >it is at the moment or will be in the future. >If anyone has any opinion I would be glad to listen to it. >Thanks a lot, > >Al > >-- >Alessandro Basili >CERN, PH/UGC >Hardware Designer > Yes and no, First create your core logic as a "headless" design with no bus interface. Make a testbench that directly drives and tests the ports of this core design. Then create a module with a wishbone interface and connections for all the ports of your core that do not connect to a higher level. Your design will consist of a wrapper containing these two modules. Copy your test suite and rewrite it to use the wishbone bus where needed. DO NOT create a wishbone interface and then place your core logic below it in the hierarchy. If you do and then later want to support a different bus then you are screwed. If you keep the wishbone in one module then it is alot easier to take that module and convert it into something like a AHB bus. You want to be able to add new buses without touching the core. John --------------------------------------- Posted through http://www.FPGARelated.com
From: Alessandro Basili on 21 Mar 2010 09:59 > Yes and no, > > First create your core logic as a "headless" design with no bus interface. > Make a testbench that directly drives and tests the ports of this core > design. > > Then create a module with a wishbone interface and connections for all the > ports of your core that do not connect to a higher level. Your design will > consist of a wrapper containing these two modules. Copy your test suite and > rewrite it to use the wishbone bus where needed. > > DO NOT create a wishbone interface and then place your core logic below it > in the hierarchy. If you do and then later want to support a different bus > then you are screwed. If you keep the wishbone in one module then it is > alot easier to take that module and convert it into something like a AHB > bus. > You want to be able to add new buses without touching the core. Hi John, I completely got your point and I'm really happy you pointed that out, because most probably I would have made a big mistake! It makes perfectly sense to me and it's surely the way I will go. Thanks again, Al p.s.: funny how very simple ideas sometimes are not so evident to all of us. -- Alessandro Basili CERN, PH/UGC Hardware Designer
From: Alessandro Basili on 21 Mar 2010 14:31 On 3/20/2010 10:46 AM, HT-Lab wrote: > > There are lots of places were you can legally download it from, if you do a > google search (amba bus protocol) then the first entry is wikipedia and the > second is: > > http://ens.ewi.tudelft.nl/Education/courses/et4351/amba.pdf > > If you read the second page it states: > > Document confidentiality status > This document is Open Access. This document has no restriction on distribution. > I just had a read to this document: http://www.opencores.org/downloads/soc_bus_comparison.pdf Apparently the wishbone seams much easier to use then the other two reported, but it seems to be it doesn't support address pipelining (as Rob already mentioned), which so far I don't have any element to evaluate whether this is a main problem or not. My main intent is to promote, or support and spread the concept of _reuse_ especially in the research world (where I belong to) where people are kind of keen to "reinvent" the wheel. I believe that a lot of efforts can be made more fruitful if a common interface would be available. Al -- Alessandro Basili CERN, PH/UGC Hardware Designer
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