From: John Larkin on


Any comments on the behavior/effects of zenering the gate of a jfet?

John

From: Jim Thompson on
On Wed, 05 May 2010 09:35:47 -0700, John Larkin
<jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote:

>
>
>Any comments on the behavior/effects of zenering the gate of a jfet?
>
>John

Depends on the current and repetitiveness. Ultimately causes
electromigration. I don't know what degrades with a JFET (maybe the
gate gets leaky), but a similarly-structured BJT loses beta.

...Jim Thompson
--
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The only thing bipartisan in this country is hypocrisy
From: whit3rd on
On May 5, 9:45 am, Jim Thompson <To-Email-Use-The-Envelope-I...(a)On-My-
Web-Site.com>
wrote:

> >Any comments on the behavior/effects of zenering the gate of a jfet?

> Depends on the current and repetitiveness.  Ultimately causes
> electromigration.  I don't know what degrades with a JFET (maybe the
> gate gets leaky), but a similarly-structured BJT loses beta.

Shouldn't it be a lot less damaging than to a BJT? There's no
surface-of-the-silicon high field involved in the JFET, and the
field direction is the same as normal bias (so none of the
precautions against surface contamination are voided).

The special-purpose two-terminal JFETs used for current regulators
are completely specified for normal operation in Zener (actually,
avalanche) breakdown. As long as you don't overheat them,
they just go back and forth across the knee indefinitely. The
JFETs in an IC amplifier, of course, might have other issues.
From: cassiope on
On May 5, 9:35 am, John Larkin
<jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote:
> Any comments on the behavior/effects of zenering the gate of a jfet?
>
> John

In the old Tek vertical amplifier inputs, Tek used a protection diode
to prevent zenering for
negative input overloads.

I've never checked to see how/whether the device conducts or not in
this mode.

Is this necessary? I'm sure most of us just copied that part,
assuming that the gates
couldn't take as much current as could be delivered by the input
current limiting resistor.
With today's presumably smaller structures, it would probably be worse
unless the
zener voltages were proportionately reduced.

HTH...
From: John Larkin on
On Fri, 7 May 2010 09:52:31 -0700 (PDT), cassiope
<fpm(a)u.washington.edu> wrote:

>On May 5, 9:35�am, John Larkin
><jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote:
>> Any comments on the behavior/effects of zenering the gate of a jfet?
>>
>> John
>
>In the old Tek vertical amplifier inputs, Tek used a protection diode
>to prevent zenering for
>negative input overloads.
>
>I've never checked to see how/whether the device conducts or not in
>this mode.
>
>Is this necessary? I'm sure most of us just copied that part,
>assuming that the gates
>couldn't take as much current as could be delivered by the input
>current limiting resistor.
>With today's presumably smaller structures, it would probably be worse
>unless the
>zener voltages were proportionately reduced.


I have a design where it's barely possible that under some transient
or startup condition I could zener a BF862 gate by a couple of hundred
uA for a short period. It's a super-sensitive node so I'd prefer not
to hang unnecessary diodes on it, or add the Johnson noise of a
resistor. The BF862 is rated for -20 and seems to zener about -24.
There's probably other knobs I can turn to keep the negative gate
voltage from getting over 20, but I was curious if anyone had any
experience, or if there was anything comparable to bipolar damage from
zenering the base.

John


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