16-bit SPI trying to read from 22-clock cycle ADC
in [Embedded]
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From: Bill on 8 Sep 2009 11:58 On Tue, 08 Sep 2009 11:23:38 -0400, Mel <mwilson(a)the-wire.com> wrote: >You have Peripheral DMA Controller, use it. I would gladly use it, but I don't think it is possible. DMA is not able neither to automatically change CSAAT (Chip Select Active After Transfer) configuration between 8-bit transactions 2 and 3, nor to bit bang CS to my needs. Best,
From: don on 8 Sep 2009 11:59 Bill wrote: > Hi, > > I'm trying to pull out data from the ADS8320 (a 16-bit ADC by Analog > Devices. See bottom of page 10 in > http://focus.ti.com/lit/ds/symlink/ads8320.pdf ) using the SPI in an > AT91SAM7S256. The problem is that the ADC needs 6 extra clock cycles > to sample the analog signal, before the 16 cycles that will output If Englich is not yuor frist langwige, have someone else read if to you. See Bottom of page 10 again ! don > each of the conversion result bits. So, a complete ADC cycle involves > a minimum of 22 clock cycles. Now, the SPI in the AT91SAM7 (and, as > far as I've seen, in all other MCUs), cannot generate more than 16 > clock cycles within one CS activation. > > How am I supposed to do this, in an elegant way? Of course I could bit > bang those lines, but I hate doing that, because it adds load to the > CPU, and doesn't take advantage of the SPI and DMA. > > The AT91SAM7S256 allows holding the CS low until a new device is > addressed, so I could initiate two 11-bit readings in a row (in such a > way that the ADC would think it is a single CS assertion with 22 clock > cycles inside), and discard the bits with no information, but that's > still ugly to me. It would use the SPI, but not the DMA, and the two > readings would be different (the first one should hold CS low. The > second one should leave it high), which is kind of non-homogeneous. > > Any more elegant ideas? > > Thank you.
From: Rich Webb on 8 Sep 2009 11:54 On Tue, 08 Sep 2009 17:23:27 +0200, Bill <a(a)a.a> wrote: >On Tue, 08 Sep 2009 09:11:13 -0500, Vladimir Vassilevsky ><nospam(a)nowhere.com> wrote: > > >>> I'm trying to pull out data from the ADS8320 (a 16-bit ADC by Analog >>> Devices. >>^^^^^^^^^^^^^^^^^^^^^^ >> >>> See bottom of page 10 in >>> http://focus.ti.com/lit/ds/symlink/ads8320.pdf ) >>^^^^^^^^^^^^^^^^^^^^^ >> >>LOL > >:-) Sorry. TI. I'm using other Analog Devices ICs. > >>Generate transactions by SPI, but control the CS signal as GPIO. >>I.e. assert the CS, read the required number of bits by SPI, deassert >>the CS. > >But still, bye bye DMA. > > >I'm very curious... what were the guys at TI (and at some other >companies) thinking when they designed this ADC with SPI interface? >Which SPI hardware were they thinking would be able to pull out data >in one transaction? Does anyone know of an MCU with SPI hardware able >to do this? Amazing. I haven't done a lot of (er, any) looking but one processor that I'm using right now has a configuration register for its SPI peripheral to do 8 to 16 bits per transfer, so two 11-bit transfers would be easy enough to set up. NXP's LPC2119/2129. No DMA in this one, but (okay, I did a little looking) the LPC24xx chips support configurable transfer lengths and DMA on their SSP peripherals. -- Rich Webb Norfolk, VA
From: Bill on 8 Sep 2009 12:15 >>I'm very curious... what were the guys at TI (and at some other >>companies) thinking when they designed this ADC with SPI interface? >>Which SPI hardware were they thinking would be able to pull out data >>in one transaction? Does anyone know of an MCU with SPI hardware able >>to do this? Amazing. > >I haven't done a lot of (er, any) looking but one processor that I'm >using right now has a configuration register for its SPI peripheral to >do 8 to 16 bits per transfer, so two 11-bit transfers would be easy >enough to set up. NXP's LPC2119/2129. No DMA in this one, but (okay, I >did a little looking) the LPC24xx chips support configurable transfer >lengths and DMA on their SSP peripherals. No, no... the ADC cannot see CS going up and then again down between two transfers, because that would reset the conversion process. That means I have to bit bang CS or change CSAAT configuration (a bit that determines whether CS remains low after each transfer) between the two transfers. And, of course, no possible DMA. So, in other words, your LPC2119 cannot do that in one transfer, either, and I doubt that the DMA in the LPC24xx will be of any use, in this problem. Best,
From: Bill on 8 Sep 2009 12:19
On Tue, 08 Sep 2009 09:59:00 -0600, don <don> wrote: >Bill wrote: >> Hi, >> >> I'm trying to pull out data from the ADS8320 (a 16-bit ADC by Analog >> Devices. See bottom of page 10 in >> http://focus.ti.com/lit/ds/symlink/ads8320.pdf ) using the SPI in an >> AT91SAM7S256. The problem is that the ADC needs 6 extra clock cycles >> to sample the analog signal, before the 16 cycles that will output > >If Englich is not yuor frist langwige, have someone else read if to you. > >See Bottom of page 10 again ! > >don I don't need English to be my first language to understand datasheets. What do you exactly mean? Which piece of information did I miss? |