16-bit SPI trying to read from 22-clock cycle ADC
in [Embedded]
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From: Bill on 8 Sep 2009 21:52 On Tue, 8 Sep 2009 09:38:27 -0700 (PDT), "langwadt(a)fonz.dk" <langwadt(a)fonz.dk> wrote: >anyhoo, have a look at the SSC instead and see if it doesn't fit your >needs better than the SPI. This is interesting. I'm taking a look at the SSC. Never used it before. Looks like it might be possible, but I'll wait to finish reading. Thanks!
From: Bill on 8 Sep 2009 22:02 On Tue, 8 Sep 2009 18:00:40 -0400, "Martin Riddle" <martin_rid(a)verizon.net> wrote: >>>If Englich is not yuor frist langwige, have someone else read if to >>>you. >>> >>>See Bottom of page 10 again ! >>> >>>don >> >> I don't need English to be my first language to understand datasheets. >> >> What do you exactly mean? Which piece of information did I miss? > >At the bottom of figure 3: > >NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are >24 clock cycles. >If CS remains LOW at the end of conversion, a new datastream with >LSB-first is shifted out again. > > > >3, 8 bit transfers. > >Cheers > That has already been proposed by others, and won't work either, without CPU intervention. Please read my other posts.
From: Bill on 8 Sep 2009 22:13 On Tue, 8 Sep 2009 14:33:44 -0700 (PDT), karthikbalaguru <karthikbalaguru79(a)gmail.com> wrote: >It appears strange. From my experience, normally TI would definitely >have some reasons for any such strange things. To be more correct, for me, it is not TI's fault. It is the fault of the designers of the SPI inside everyday MCUs. Knowing that there are 16/18/20/22/24-bit ADCs/DACs around, and that they need extra clock cycles for the sampling phase, what are they waiting to implement SPIs that can handle say 32 bits in a single transfer? I don't understand it. It would be a few microdollars more of silicon. >In this scenario, bit banging appears reasonable. Well, that might >increase the CPU load. Yes, I'm bit banging. The ADC could work up to 100 ksa/s. Thank god I'm not going that high, because in that case the CPU could do nothing else. >The best help would be from the TI support. Yes, I'm curious to ask them. Best,
From: Bill on 8 Sep 2009 22:22 On Wed, 09 Sep 2009 03:47:42 +0200, Bill <a(a)a.a> wrote: >You must be seeing a single transfer there (in your 24 clock cycles). Disregard this sentence. It makes no sense. I was thinking about my ADC. I don't know why you are seeing that. Maybe you have CSAAT set, and you are switching between different devices?
From: Martin Riddle on 8 Sep 2009 23:16
"Bill" <a(a)a.a> wrote in message news:ji2ea5pbcg12us9vbfo0op6cocfkugk7f2(a)4ax.com... > On Tue, 8 Sep 2009 18:00:40 -0400, "Martin Riddle" > <martin_rid(a)verizon.net> wrote: > >>>>If Englich is not yuor frist langwige, have someone else read if to >>>>you. >>>> >>>>See Bottom of page 10 again ! >>>> >>>>don >>> >>> I don't need English to be my first language to understand >>> datasheets. >>> >>> What do you exactly mean? Which piece of information did I miss? >> >>At the bottom of figure 3: >> >>NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown >>are >>24 clock cycles. >>If CS remains LOW at the end of conversion, a new datastream with >>LSB-first is shifted out again. >> >> >> >>3, 8 bit transfers. >> >>Cheers >> > > That has already been proposed by others, and won't work either, > without CPU intervention. Please read my other posts. What about CSAAT ? Setting it allows the CS to stay low until another CS is selected. Cheers |