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From: alessandro.strazzero on 4 Aug 2010 14:10
Dear everybody,

I'm a beginner in using the VHDL and I'm experiencing some problems
during the testing
phase. I have developped a small VHDL model based on an Altera Cyclone
FPGA and,
using ModelSim, I have tested it in simulation mode. The results from
simulation were goods, so I decided to synthesize the model and test
it on the FPGA.

With my surprise, the model doesn't work well as in ModelSim and I
don't understand the
reasons. Without to deeply face the problem by analysing the code,
based on your skill,
could you suggest me some guidelines where to search for the
problems ? Maybe I have
not applied some important "good rules" to synthesize the model, or
whatelse an expert
hardware man can imagine ...

I have synthesized the model using the latest version of Quartus II
and the message
window did not report some critical warnings during the compilation.

Best Regards

/Alessandro

From: Jon Elson on 4 Aug 2010 15:17
alessandro.strazzero(a)gmail.com wrote:
> Dear everybody,
>
> I'm a beginner in using the VHDL and I'm experiencing some problems
> during the testing
> phase. I have developped a small VHDL model based on an Altera Cyclone
> FPGA and,
> using ModelSim, I have tested it in simulation mode. The results from
> simulation were goods, so I decided to synthesize the model and test
> it on the FPGA.
>
> With my surprise, the model doesn't work well as in ModelSim and I
> don't understand the
> reasons. Without to deeply face the problem by analysing the code,
> based on your skill,
> could you suggest me some guidelines where to search for the
> problems ? Maybe I have
> not applied some important "good rules" to synthesize the model, or
> whatelse an expert
> hardware man can imagine ...
The simulation cannot have timing violations or the analog behavior of
signals. The real world implementation is subject to these effects.
You may have electrical noise issues either on the power supply, clocks
or I/O signals, or a timing violation on inputs coming into the logic.
If you have inputs that are not synchronized with the internal FPGA
clock, it can have disastrous results on the stability of state machines
and similar bus control logic. You do this by specifying a register on
the raw input signal, then the internal logic only uses the output of
that register, never the raw I/O signal. If the timing between the
external device and the FPGA is completely asynchronous, it is best to
use TWO sets of synchronizers to avoid metastability conditions where
the input changes just as the FF is sampling.

Jon
From: John Adair on 4 Aug 2010 15:40
First thing to check is that you have set some basic timing, and pin
location, constraints in quartus.You can do this under the Assignments
menu in Quartus.

Second thing to check is that you have not relyed on sensitivity list
gating. Simulators tend to follow the standard in this. Synthesisers
usually ignore sensitivity lists.

Third if you have more than one clock domain in your design check that
your data/signal passing is done in a way to guarantee operation. Lots
of posts on clock domain crossing in this news group.

John Adair
Enterpoint Ltd.- Home of Drigmorn4. The Spartan-6 Embedded Processor
Board.


On 4 Aug, 19:10, "alessandro.strazz...(a)gmail.com"
<alessandro.strazz...(a)gmail.com> wrote:
> Dear everybody,
>
> I'm a beginner in using the VHDL and I'm experiencing some problems
> during the testing
> phase. I have developped a small VHDL model based on an Altera Cyclone
> FPGA and,
> using ModelSim, I have tested it in simulation mode. The results from
> simulation were goods, so I decided to synthesize the model and test
> it on the FPGA.
>
> With my surprise, the model doesn't work well as in ModelSim and I
> don't understand the
> reasons. Without to deeply face the problem by analysing the code,
> based on your skill,
> could you suggest me some guidelines where to search for the
> problems ? Maybe I have
> not applied some important "good rules" to synthesize the model, or
> whatelse an expert
> hardware man can imagine ...
>
> I have synthesized the model using the latest version of Quartus II
> and the message
> window did not report some critical warnings during the compilation.
>
> Best Regards
>
> /Alessandro

From: Mike Treseler on 6 Aug 2010 10:29
On 8/4/2010 11:10 AM, alessandro.strazzero(a)gmail.com wrote:

> With my surprise, the model doesn't work well as in ModelSim and I
> don't understand the
> reasons.
> could you suggest me some guidelines where to search for the
> problems ?

You might also have a look at the rtl viewer for missing wires or flops.

-- Mike Treseler


From: Ammar2k on 7 Aug 2010 10:27
All above points are gud.

one more point i would like to add.

Run Post-Synthesis Simulation

or

Post-Place-and-Route Simulation on your design

(on Xilinx ISE its possible, dont know about other softwares)

and check if post-synthesis results are still the same with RTL Simulation
Results,

if they are not consistent with each other, you need to debug your code
again.. if they are consistent, then probablly there are more physical
issues as discussed by others

regards
Ammar

>On 8/4/2010 11:10 AM, alessandro.strazzero(a)gmail.com wrote:
>
>> With my surprise, the model doesn't work well as in ModelSim and I
>> don't understand the
>> reasons.
>> could you suggest me some guidelines where to search for the
>> problems ?
>
>You might also have a look at the rtl viewer for missing wires or flops.
>
> -- Mike Treseler
>
>
>



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