From: gopal_amlekar on
Hello,

I want to configure an FPGA (Altera Cyclone II) using JTAG programming
method via USB. I have done a design using a PIC18F2550 and succedded in
configuring Xilinx FPGA. I want to do the same thing fo Altera devices.

Has anybody done that previously? The point where I am stuck is, I don't
know the internal file formats of Altera files (e.g. rbf or sof files etc.)
I need information about header and other details in the altera file. So I
can skip them and transmit only the configuration data on JTAG to the
FPGA.

Specifically, if anyone can guide me about the file formats of Altera, I
will be thankful.

Thanking in advance..
Regards,
Gopal Amlekar



From: Rob on
You might be better off using the PIC (or whatever mirco/processor)
implement the serial programming. This method is well documented and
very straightforward to implement. I'm not sure Altera publishes
anything allowing you to configure using JTAG, other than their
proprietary ByteBlaster, etc.



gopal_amlekar wrote:
> Hello,
>
> I want to configure an FPGA (Altera Cyclone II) using JTAG programming
> method via USB. I have done a design using a PIC18F2550 and succedded in
> configuring Xilinx FPGA. I want to do the same thing fo Altera devices.
>
> Has anybody done that previously? The point where I am stuck is, I don't
> know the internal file formats of Altera files (e.g. rbf or sof files etc.)
> I need information about header and other details in the altera file. So I
> can skip them and transmit only the configuration data on JTAG to the
> FPGA.
>
> Specifically, if anyone can guide me about the file formats of Altera, I
> will be thankful.
>
> Thanking in advance..
> Regards,
> Gopal Amlekar
>
>
>
From: gopal_amlekar on
Hello,

Thanks for reply.

Reason for using JTAG is: I am already using this PIC18 to configure a
Xilinx FPGA on JTAG. So the JTAG low level protocol is ready. I could
decode Xilinx bit file. With Altera, what remanis is only extracting the
actual configuration data from the rbf (or any other) file. For any other
configuration scheme, I may have to carry out some hardware change too..

If you or anyone has some clue about rbf file format, that will be very
much useful. JRunner software from Altera shows first 44 bytes is the
header in rbf file. So does it meant that from 45th byte onwards,
everything else is configuration data?

Regards,

>You might be better off using the PIC (or whatever mirco/processor)
>implement the serial programming. This method is well documented and
>very straightforward to implement. I'm not sure Altera publishes
>anything allowing you to configure using JTAG, other than their
>proprietary ByteBlaster, etc.
>


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From: Antti on
On Dec 25, 7:37 am, "gopal_amlekar" <gopal_amle...(a)yahoo.com> wrote:
> Hello,
>
> Thanks for reply.
>
> Reason for using JTAG is: I am already using this PIC18 to configure a
> Xilinx FPGA on JTAG. So the JTAG low level protocol is ready. I could
> decode Xilinx bit file. With Altera, what remanis is only extracting the
> actual configuration data from the rbf (or any other) file. For any other
> configuration scheme, I may have to carry out some hardware change too..
>
> If you or anyone has some clue about rbf file format, that will be very
> much useful. JRunner software from Altera shows first 44 bytes is the
> header in rbf file. So does it meant that from 45th byte onwards,
> everything else is configuration data?
>
> Regards,
>
> >You might be better off using the PIC (or whatever mirco/processor)
> >implement the serial programming.  This method is well documented and
> >very straightforward to implement.  I'm not sure Altera publishes
> >anything allowing you to configure using JTAG, other than their
> >proprietary ByteBlaster, etc.
>
> ---------------------------------------        
> This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com

RBF is raw binary
so there is no in detail description of it, same as BIT file
you take the file and use it as RAW data

Antti