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From: wzab on 25 Dec 2009 17:50
I have found the following discussion:
http://www.velocityreviews.com/forums/t487026-vhdl-port-inout-problem.html

And according to the solution decribed there, I set ALL fields (elements)
of the record in ALL processes. If the particular process does not drive
the particular signal, I set it to "Z".

This solution works, however I'm afraid that setting a signal to 'Z' in any
place instead of ports of top entity may confuse the synthesis tools...

Does any of you have any experiences with such a problem?
--
TIA
WZab
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