An other Microchip screwup on teh 18F14K22
in [Design]
|
From: Nico Coesel on 8 May 2010 11:10 John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Fri, 07 May 2010 14:16:26 -0400, Spehro Pefhany ><speffSNIP(a)interlogDOTyou.knowwhat> wrote: > >>On Fri, 07 May 2010 09:27:35 -0700, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>> >>>That's pretty bad. But uPs are getting so complex, so overloaded with >>>features, that the designers are sort of shoveling hunks of home-made >>>or purchased IP into compilers and hoping for the best. And, >>>apparently, not taking much time to simulate and verify. Or document! >>>We had to do a bunch of experiments on the SPI interface on our NXP >>>ARMs; even high-level support people couldn't answer some fundamental >>>timing/framing questions. The SPI and ADC documentation is awful. >>> >>>We use ARM chips that have 30-character pin names, the pin functions >>>are so overloaded. >> >>Who's are you using now? We're getting going with the Luminary parts. > >NXP 80 and 100-pin parts, LPC1758 and LPC1768. We have one 12-channel >4-20 mA thing that has an ARM per floating channel... 13 CPUs on one >VME board. > >What we really want for another project is a faster (500 MHz?) chip >with gigabit ethernet. NXP doesn't have anything quite yet. Marvell >looks good technically but they sort of discourage sub-megapart >customers. Freescale PowerPC looks pretty good. We'll have to decide >soon. Did you look into the IMX series from Freescale? Or the ARM SoCs from Samsung? Very cost effective. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico(a)nctdevpuntnl (punt=.) --------------------------------------------------------------
From: nospam on 8 May 2010 12:23 Jan Panteltje <pNaonStpealmtje(a)yahoo.com> wrote: >>>When I bought the Z80, in the 19 eighties, a chip that has a much >>>more complicated instruction set, but much easier to use, it worked on all advertised issues. >> >>A Z80 system with the features of the PIC18F14K22 would have taken a square >>foot of PCB stuffed full of chips, take 100 times more power to run at less >>than 1/4 the speed. Silly comparison. > >No it is not silly, is is comparing quality of chip design. The Z80 did have at least one bug incorrectly setting the parity flag for some instructions when an interrupt acknowledge cycle occurs. Dividing the complexity of the silicon by the number of defects the PIC design looks about 10 times higher quality.
From: Jan Panteltje on 8 May 2010 12:45 On a sunny day (Sat, 08 May 2010 17:23:23 +0100) it happened nospam <nospam(a)please.invalid> wrote in <5d3bu5t8v54h9k3a9nrasrco5pjlcidvi9(a)4ax.com>: >Jan Panteltje <pNaonStpealmtje(a)yahoo.com> wrote: > >>>>When I bought the Z80, in the 19 eighties, a chip that has a much >>>>more complicated instruction set, but much easier to use, it worked on all advertised issues. >>> >>>A Z80 system with the features of the PIC18F14K22 would have taken a square >>>foot of PCB stuffed full of chips, take 100 times more power to run at less >>>than 1/4 the speed. Silly comparison. >> >>No it is not silly, is is comparing quality of chip design. > >The Z80 did have at least one bug incorrectly setting the parity flag for >some instructions when an interrupt acknowledge cycle occurs. > >Dividing the complexity of the silicon by the number of defects the PIC >design looks about 10 times higher quality. The Z80 worked as specified, the PIC does not works in its much advertised mode of SPI. And I2C. Maybe you think SPI and I2C are new, well, I was one of the first users of I2c in those same eighties. Philips had no problem implementing I2c in hardware at that time.
From: John Larkin on 8 May 2010 13:26 On Sat, 08 May 2010 15:10:31 GMT, nico(a)puntnl.niks (Nico Coesel) wrote: >John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Fri, 07 May 2010 14:16:26 -0400, Spehro Pefhany >><speffSNIP(a)interlogDOTyou.knowwhat> wrote: >> >>>On Fri, 07 May 2010 09:27:35 -0700, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>> >>>>That's pretty bad. But uPs are getting so complex, so overloaded with >>>>features, that the designers are sort of shoveling hunks of home-made >>>>or purchased IP into compilers and hoping for the best. And, >>>>apparently, not taking much time to simulate and verify. Or document! >>>>We had to do a bunch of experiments on the SPI interface on our NXP >>>>ARMs; even high-level support people couldn't answer some fundamental >>>>timing/framing questions. The SPI and ADC documentation is awful. >>>> >>>>We use ARM chips that have 30-character pin names, the pin functions >>>>are so overloaded. >>> >>>Who's are you using now? We're getting going with the Luminary parts. >> >>NXP 80 and 100-pin parts, LPC1758 and LPC1768. We have one 12-channel >>4-20 mA thing that has an ARM per floating channel... 13 CPUs on one >>VME board. >> >>What we really want for another project is a faster (500 MHz?) chip >>with gigabit ethernet. NXP doesn't have anything quite yet. Marvell >>looks good technically but they sort of discourage sub-megapart >>customers. Freescale PowerPC looks pretty good. We'll have to decide >>soon. > >Did you look into the IMX series from Freescale? Or the ARM SoCs from >Samsung? Very cost effective. Do any of the Samsungs have GbE? I'll have my guys look into them. Marvell is coming around, after some pressure from the distributor and a lucky contact at the Embedded System Conference. But their eval board is $4K, presumably mostly earnest money. John
From: krw on 8 May 2010 14:01
On Sat, 08 May 2010 10:26:59 -0700, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sat, 08 May 2010 15:10:31 GMT, nico(a)puntnl.niks (Nico Coesel) >wrote: > >>John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Fri, 07 May 2010 14:16:26 -0400, Spehro Pefhany >>><speffSNIP(a)interlogDOTyou.knowwhat> wrote: >>> >>>>On Fri, 07 May 2010 09:27:35 -0700, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>> >>>>>That's pretty bad. But uPs are getting so complex, so overloaded with >>>>>features, that the designers are sort of shoveling hunks of home-made >>>>>or purchased IP into compilers and hoping for the best. And, >>>>>apparently, not taking much time to simulate and verify. Or document! >>>>>We had to do a bunch of experiments on the SPI interface on our NXP >>>>>ARMs; even high-level support people couldn't answer some fundamental >>>>>timing/framing questions. The SPI and ADC documentation is awful. >>>>> >>>>>We use ARM chips that have 30-character pin names, the pin functions >>>>>are so overloaded. >>>> >>>>Who's are you using now? We're getting going with the Luminary parts. >>> >>>NXP 80 and 100-pin parts, LPC1758 and LPC1768. We have one 12-channel >>>4-20 mA thing that has an ARM per floating channel... 13 CPUs on one >>>VME board. >>> >>>What we really want for another project is a faster (500 MHz?) chip >>>with gigabit ethernet. NXP doesn't have anything quite yet. Marvell >>>looks good technically but they sort of discourage sub-megapart >>>customers. Freescale PowerPC looks pretty good. We'll have to decide >>>soon. >> >>Did you look into the IMX series from Freescale? Or the ARM SoCs from >>Samsung? Very cost effective. > >Do any of the Samsungs have GbE? I'll have my guys look into them. > >Marvell is coming around, after some pressure from the distributor and >a lucky contact at the Embedded System Conference. But their eval >board is $4K, presumably mostly earnest money. $4K?! They really don't want business. |